Difference between revisions of "People"

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= Researchers at the Intel-UPC Barcelona Research Center<br>  =
 
= Researchers at the Intel-UPC Barcelona Research Center<br>  =
  
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Qiong Cai was born in Shanghai, China on 15 December, 1976. He went to Australia in 1997 for his bachelor study, and graduated from University of Wollongong in 2000 with Bachelor of Computer Science and Bachelor of Mathematics. He continued his study in University of New South Wales as an honours student supervised by Professor Jingling Xue and graduated with Bachelor of Computer Science (the first class honours) in 2001. He pursued his PHD research in compilers under the supervision of Professor Jingling Xue in 2002 and received the degree in 2006. The title of thesis is profile-guided redundancy elimination. Since July of 2005 he has been working as a Sr. Research Scientist in the Intel Barcelona Research Center. '''''Contact him at qiongx.cai(at)intel.com'''''  
 
Qiong Cai was born in Shanghai, China on 15 December, 1976. He went to Australia in 1997 for his bachelor study, and graduated from University of Wollongong in 2000 with Bachelor of Computer Science and Bachelor of Mathematics. He continued his study in University of New South Wales as an honours student supervised by Professor Jingling Xue and graduated with Bachelor of Computer Science (the first class honours) in 2001. He pursued his PHD research in compilers under the supervision of Professor Jingling Xue in 2002 and received the degree in 2006. The title of thesis is profile-guided redundancy elimination. Since July of 2005 he has been working as a Sr. Research Scientist in the Intel Barcelona Research Center. '''''Contact him at qiongx.cai(at)intel.com'''''  
  
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| colspan="2" | Javier Carretero
 
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Javier Carretero received the MS degree in Computer Engineering from the Universitat Politècnica de Catalunya (UPC) at Barcelona, Spain, in 2005. Since April 2006, he is a research scientist of the Intel Barcelona Research Center. He is currently doing the PhD in the UPC-Barcelona on the area of resiliency. His main research interests include processor microarchitecture, hardware reliability, and lighteight on-line testing. '''''Contact him at javierx.carretero.casado(at)intel.com'''''  
 
Javier Carretero received the MS degree in Computer Engineering from the Universitat Politècnica de Catalunya (UPC) at Barcelona, Spain, in 2005. Since April 2006, he is a research scientist of the Intel Barcelona Research Center. He is currently doing the PhD in the UPC-Barcelona on the area of resiliency. His main research interests include processor microarchitecture, hardware reliability, and lighteight on-line testing. '''''Contact him at javierx.carretero.casado(at)intel.com'''''  
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*'''Enric Gibert'''
  
 
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| [[Image:Foto egibert.jpg|left|75px]]  
 
| [[Image:Foto egibert.jpg|left|75px]]  
 
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*'''Enric Gibert'''
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Enric Gibert received the bachelor and M.S. degrees in Computer Engineering from Enginyeria i Arquitectura La Salle (Universitat Ramon Llull) in 1995 and 1998 respectively. From 1996 to 2000, he was a professor of the Departament d'Informàtica of Enginyeria i Arquitectura La Salle, teaching on topics related to digital systems, operating systems and information systems. In September 2000 he joined the Departament d'Arquitectura de Computadors (Universitat Politècnica de Catalunya) to pursue a PhD degree under the supervision of Antonio González and Jesús Sánchez and graduated in November 2005. In March 2005, he joined the Intel Barcelona Research Center (IBRC) as a senior research scientist. His main research interests are on the area of processor microarchitecture and compilation techniques, with special emphasis on memory hierarchy, dynamic binary optimization, and instruction and thread level parallelism. '''''Contact him at enric.gibert.codina(at)intel.com'''''  
  
Enric Gibert received the bachelor and M.S. degrees in Computer Engineering from Enginyeria i Arquitectura La Salle (Universitat Ramon Llull) in 1995 and 1998 respectively. From 1996 to 2000, he was a professor of the Departament d'Informàtica of Enginyeria i Arquitectura La Salle, teaching on topics related to digital systems, operating systems and information systems. In September 2000 he joined the Departament d'Arquitectura de Computadors (Universitat Politècnica de Catalunya) to pursue a PhD degree under the supervision of Antonio González and Jesús Sánchez and graduated in November 2005. In March 2005, he joined the Intel Barcelona Research Center (IBRC) as a senior research scientist. His main research interests are on the area of processor microarchitecture and compilation techniques, with special emphasis on memory hierarchy, dynamic binary optimization, and instruction and thread level parallelism. '''''Contact him at enric.gibert.codina(at)intel.com'''''  
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*'''Fernando Latorre'''
  
 
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| [[Image:Foto flatorre.jpg|left|75px]]  
 
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*'''Fernando Latorre'''
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Fernando Latorre received the MS degree in Computer Engineering from the Centro Politécnico Superior of the Zaragoza university at Zaragoza, Spain, in 2001. In May 2001 he joined the Departament d'Arquitectura de Computadors (Universitat Politècnica de Catalunya) to pursue a PhD degree on the area of clustered multithreaded processors. Since March 2003, he is a research scientist at the Intel Barcelona Research Center. He is currently finalizing his PhD that is expected to be presented beginning of 2009. His main research interests are in multi-core architectures, thread-level parallelism and dynamic binary optimization.'''''Contact him at fernando.latorre(at)intel.com'''''  
  
Fernando Latorre received the MS degree in Computer Engineering from the Centro Politécnico Superior of the Zaragoza university at Zaragoza, Spain, in 2001. In May 2001 he joined the Departament d'Arquitectura de Computadors (Universitat Politècnica de Catalunya) to pursue a PhD degree on the area of clustered multithreaded processors. Since March 2003, he is a research scientist at the Intel Barcelona Research Center. He is currently finalizing his PhD that is expected to be presented beginning of 2009. His main research interests are in multi-core architectures, thread-level parallelism and dynamic binary optimization.'''''Contact him at fernando.latorre(at)intel.com'''''  
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*'''Carlos Madriles'''
  
 
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| [[Image:Foto cmadrile.jpg|left|75px]]  
 
| [[Image:Foto cmadrile.jpg|left|75px]]  
 
|  
 
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*'''Carlos Madriles'''
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Carlos Madriles received the MS degree in Computer Engineering from the Universitat Politècnica de Catalunya (UPC) at Barcelona, Spain, in 2002. He joined the Dept. of Computer Architecture of the UPC-Barcelona in 2001 as a research assistant. Since May 2002, he is a research scientist of the Intel Barcelona Research Center. He is currently doing the PhD in the UPC-Barcelona on the area of speculative thread-level parallelism. His current research interests are in multi-core architectures and compilation techniques, with special emphasis in speculative multithreading and transactional memory. '''''Contact him at carlos.madriles.gimeno(at)intel.com'''''  
  
Carlos Madriles received the MS degree in Computer Engineering from the Universitat Politècnica de Catalunya (UPC) at Barcelona, Spain, in 2002. He joined the Dept. of Computer Architecture of the UPC-Barcelona in 2001 as a research assistant. Since May 2002, he is a research scientist of the Intel Barcelona Research Center. He is currently doing the PhD in the UPC-Barcelona on the area of speculative thread-level parallelism. His current research interests are in multi-core architectures and compilation techniques, with special emphasis in speculative multithreading and transactional memory. '''''Contact him at carlos.madriles.gimeno(at)intel.com'''''  
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*'''Alejandro Martínez'''
  
 
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| [[Image:Foto amartinez.jpg|left|75px]]  
 
| [[Image:Foto amartinez.jpg|left|75px]]  
 
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*'''Alejandro Martínez'''
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Alejandro Martínez received the MS degree in computer science and the PhD degree from the University of Castilla-La Mancha in 2003 and 2007, respectively. He is currently with the Intel Barcelona Research Center. His research interests include high-performance interconnections, quality of service, high-performance computing, and processor microarchitecture. '''''Contact him at alejandrox.martinez(at)intel.com'''''  
  
Alejandro Martínez received the MS degree in computer science and the PhD degree from the University of Castilla-La Mancha in 2003 and 2007, respectively. He is currently with the Intel Barcelona Research Center. His research interests include high-performance interconnections, quality of service, high-performance computing, and processor microarchitecture. '''''Contact him at alejandrox.martinez(at)intel.com'''''  
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*'''Raúl Martínez'''
  
 
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| [[Image:Foto rmartinez.jpg|left|75px]]  
 
| [[Image:Foto rmartinez.jpg|left|75px]]  
 
|  
 
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*'''Raúl Martínez'''
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Raúl Martínez received the MS degree in computer science from the University of Castilla-La Mancha in 2003 and the PhD degree from the University of Castilla-La Mancha in 2007. He is currently a researcher in the Intel Barcelona Research Center. His research interests include high performance local area networks, quality of service (QoS), design of high-performance switches, and processor microarchitecture. '''''Contact him at raulm(at)ac.upc.edu'''''  
  
Raúl Martínez received the MS degree in computer science from the University of Castilla-La Mancha in 2003 and the PhD degree from the University of Castilla-La Mancha in 2007. He is currently a researcher in the Intel Barcelona Research Center. His research interests include high performance local area networks, quality of service (QoS), design of high-performance switches, and processor microarchitecture. '''''Contact him at raulm(at)ac.upc.edu'''''  
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*'''Xavi Vera'''
  
 
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*'''Xavi Vera'''
 
 
 
Xavier Vera received the M.S. degree in Computer Science in 2000 from Universitat Politecnica de Catalunya (UPC) at Barcelona (Spain). In July 2000, Xavier continued his studies in Sweden advised by Björn Lisper. He obtained his PhD from Mälardalens Högskola at Västerås (Sweden) in January, 2004. The title of the thesis was [http://www.mrtc.mdh.se/index.php?choice=publications&id=0603 ''Cache and Compiler Interaction (how to analyze, optimize and time cache behavior''], in collaboration with professor Jingling Xue from UNSW, Sydney (Australia), where Xavier spent 1.5 years. Xavier has been with Intel since February 2004, participating in research in the area of reliable and variations-aware microarchitectures. '''Contact him at xavier.vera(at)intel.com'''  
 
Xavier Vera received the M.S. degree in Computer Science in 2000 from Universitat Politecnica de Catalunya (UPC) at Barcelona (Spain). In July 2000, Xavier continued his studies in Sweden advised by Björn Lisper. He obtained his PhD from Mälardalens Högskola at Västerås (Sweden) in January, 2004. The title of the thesis was [http://www.mrtc.mdh.se/index.php?choice=publications&id=0603 ''Cache and Compiler Interaction (how to analyze, optimize and time cache behavior''], in collaboration with professor Jingling Xue from UNSW, Sydney (Australia), where Xavier spent 1.5 years. Xavier has been with Intel since February 2004, participating in research in the area of reliable and variations-aware microarchitectures. '''Contact him at xavier.vera(at)intel.com'''  
  

Revision as of 11:34, 20 October 2008

Professors

  • Antonio González (Research Group Leader)
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Antonio Gonzalez received his M.S. and Ph.D. degrees from the Universitat Politècnica de Catalunya (UPC), in Barcelona, Spain. He is the founding director of the Intel Barcelona Research Center, whose research focuses on new microarchitecture paradigms and code generation techniques for future microprocessors. He joined the faculty of the Computer Architecture Department of UPC in 1986 and became a Full Professor in 2002. He currently leads the ARCO research group and holds a part-time Professor position at this department. Contact him at antonio(at)ac.upc.edu

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Carles Aliagas recieved his M.S degree from the the Universitat Politècnica de Catalunya (UPC), in Barcelona, Spain. He joined the Computer Science and Mathematics Department of Rovira i Virgili University in Tarragona where he is currently working as an associate professor. His areas of interest are computer architecture, operating systems and parallelism. His research is focused on memory hierarchies for microprocessors.
Contact him at carles.aliagas(at)urv.net

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Ramon Canal received his M.S. and Ph.D. degrees from the Universitat Politècnica de Catalunya (UPC), in Barcelona, Catalonia, EU. He joined the faculty of the Computer Architecture Department of UPC in 2003 where he is currently an associate professor. He finished his M.S. in the University of Bath (UK), worked at Sun Microsystems in 2000, and was a Fulbright visiting scholar at Harvard University in the 2006/2007 school year. His research focuses mostly on power and thermal aware architectures, as well as reliability. Contact him at rcanal(at)ac.upc.edu

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Associate Professor in Computer Architecture at Rovira i Virgili University of Tarragona, Spain. In 1996, he received a M.Sc. in Computer Engineering from the Universitat Politècnica de Catalunya (UPC), Barcelona, Spain. He also obtained the PhD degree in Computer Sciences from de Computer Architecture Department at the Universitat Politècnica de Catalunya, in 2005. His research was focused on multithreading architectures and data value reuse for superscalar processors. He is currently working on Chip Multiprocessors. Contact him at carlos.molina(at)urv.net

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Joan-Manuel Parcerisa received his M.S. and Ph.D. degrees in Computer Science from the Universitat Politècnica de Catalunya (UPC), in Barcelona, Spain, in 1993 and 2004 respectively. Since 1994 he is a professor at the Computer Architecture Department in the Universitat Politècnica de Catalunya. His current research topics include clustered microarchitectures, multithreading, and cache memory. Contact him at jmanel(at)ac.upc.edu

Researchers at the Intel-UPC Barcelona Research Center

  • Antonio Gonzalez (Research Group Leader)
Foto antonio.jpg

Antonio Gonzalez received his M.S. and Ph.D. degrees from the Universitat Politecnica de Catalunya (UPC), in Barcelona, Spain. He is the founding director of the Intel Barcelona Research Center, whose research focuses on new microarchitecture paradigms and code generation techniques for future microprocessors. He joined the faculty of the Computer Architecture Department of UPC in 1986 and became a Full Professor in 2002. He currently leads the ARCO research group and holds a part-time Professor position at this department. Contact him at antonio.gonzalez(at)intel.com

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Jaume Abella received his B.S., M.S. and Ph.D. degrees in Computer Science from the UPC (Spain). He was a research assistant at the UPC from 1999 to 2005. Currently he is a senior research scientist at the Intel Barcelona Research Center (since 2005). Jaume Abella received the award to the best thesis in Information and Communication Technologies at the UPC in 2005, and achieved the 1st rank in the M.S. and B.S. at the UPC in 2002 and 2000 respectively. His main research interests are hardware reliability and low-power designs.Contact him at jaume.abella(at)intel.com

  • Qiong Cai
Foto qiongcai.jpg

Qiong Cai was born in Shanghai, China on 15 December, 1976. He went to Australia in 1997 for his bachelor study, and graduated from University of Wollongong in 2000 with Bachelor of Computer Science and Bachelor of Mathematics. He continued his study in University of New South Wales as an honours student supervised by Professor Jingling Xue and graduated with Bachelor of Computer Science (the first class honours) in 2001. He pursued his PHD research in compilers under the supervision of Professor Jingling Xue in 2002 and received the degree in 2006. The title of thesis is profile-guided redundancy elimination. Since July of 2005 he has been working as a Sr. Research Scientist in the Intel Barcelona Research Center. Contact him at qiongx.cai(at)intel.com

Javier Carretero
Foto jcarrete.jpg
  • Javier Carretero

Javier Carretero received the MS degree in Computer Engineering from the Universitat Politècnica de Catalunya (UPC) at Barcelona, Spain, in 2005. Since April 2006, he is a research scientist of the Intel Barcelona Research Center. He is currently doing the PhD in the UPC-Barcelona on the area of resiliency. His main research interests include processor microarchitecture, hardware reliability, and lighteight on-line testing. Contact him at javierx.carretero.casado(at)intel.com

  • Enric Gibert
Foto egibert.jpg

Enric Gibert received the bachelor and M.S. degrees in Computer Engineering from Enginyeria i Arquitectura La Salle (Universitat Ramon Llull) in 1995 and 1998 respectively. From 1996 to 2000, he was a professor of the Departament d'Informàtica of Enginyeria i Arquitectura La Salle, teaching on topics related to digital systems, operating systems and information systems. In September 2000 he joined the Departament d'Arquitectura de Computadors (Universitat Politècnica de Catalunya) to pursue a PhD degree under the supervision of Antonio González and Jesús Sánchez and graduated in November 2005. In March 2005, he joined the Intel Barcelona Research Center (IBRC) as a senior research scientist. His main research interests are on the area of processor microarchitecture and compilation techniques, with special emphasis on memory hierarchy, dynamic binary optimization, and instruction and thread level parallelism. Contact him at enric.gibert.codina(at)intel.com

  • Fernando Latorre
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Fernando Latorre received the MS degree in Computer Engineering from the Centro Politécnico Superior of the Zaragoza university at Zaragoza, Spain, in 2001. In May 2001 he joined the Departament d'Arquitectura de Computadors (Universitat Politècnica de Catalunya) to pursue a PhD degree on the area of clustered multithreaded processors. Since March 2003, he is a research scientist at the Intel Barcelona Research Center. He is currently finalizing his PhD that is expected to be presented beginning of 2009. His main research interests are in multi-core architectures, thread-level parallelism and dynamic binary optimization.Contact him at fernando.latorre(at)intel.com

  • Carlos Madriles
Foto cmadrile.jpg

Carlos Madriles received the MS degree in Computer Engineering from the Universitat Politècnica de Catalunya (UPC) at Barcelona, Spain, in 2002. He joined the Dept. of Computer Architecture of the UPC-Barcelona in 2001 as a research assistant. Since May 2002, he is a research scientist of the Intel Barcelona Research Center. He is currently doing the PhD in the UPC-Barcelona on the area of speculative thread-level parallelism. His current research interests are in multi-core architectures and compilation techniques, with special emphasis in speculative multithreading and transactional memory. Contact him at carlos.madriles.gimeno(at)intel.com

  • Alejandro Martínez
Foto amartinez.jpg

Alejandro Martínez received the MS degree in computer science and the PhD degree from the University of Castilla-La Mancha in 2003 and 2007, respectively. He is currently with the Intel Barcelona Research Center. His research interests include high-performance interconnections, quality of service, high-performance computing, and processor microarchitecture. Contact him at alejandrox.martinez(at)intel.com

  • Raúl Martínez
Foto rmartinez.jpg

Raúl Martínez received the MS degree in computer science from the University of Castilla-La Mancha in 2003 and the PhD degree from the University of Castilla-La Mancha in 2007. He is currently a researcher in the Intel Barcelona Research Center. His research interests include high performance local area networks, quality of service (QoS), design of high-performance switches, and processor microarchitecture. Contact him at raulm(at)ac.upc.edu

  • Xavi Vera
Foto xvera.jpg

Xavier Vera received the M.S. degree in Computer Science in 2000 from Universitat Politecnica de Catalunya (UPC) at Barcelona (Spain). In July 2000, Xavier continued his studies in Sweden advised by Björn Lisper. He obtained his PhD from Mälardalens Högskola at Västerås (Sweden) in January, 2004. The title of the thesis was Cache and Compiler Interaction (how to analyze, optimize and time cache behavior, in collaboration with professor Jingling Xue from UNSW, Sydney (Australia), where Xavier spent 1.5 years. Xavier has been with Intel since February 2004, participating in research in the area of reliable and variations-aware microarchitectures. Contact him at xavier.vera(at)intel.com

PhD Students

Foto aaleta.jpg
  • Alex Aletà

Alex Aletà finished a Masters degree in Mathematics in the Universitat Politècnica de Catalunya (UPC) in june 2000. In October 2000 I started the PhD in Computer Architecture with Professor Antonio González in the same university. Since then, I have been working on instruction scheduling and code optimization for clustered VLIW architectures. In particular, I have been working on Modulo Scheduling. We have proposed graph partitioning techniques to address cluster assignment and we have optimized scheduling and spill code schemes. I will be graduating in December 2008. Contact him at aaleta(at)ac.upc.edu

Foto ibhagat.jpg
  • Indu Bhagat

2000 - 2004 : Bachelor of Technology in Computer Science and Engineering from Institute of Technology, Banaras Hindu University, India. 2004 - 2005 : Software Engineer at Globallogic, India. 2006 - till date : PhD Student. Currently working with Enric Gibert and Jesus Sanchez. Research Interests include code optimizations for energy-efficient architectures, and co-desinged virtual machines. Contact him at indu.bhagat(at)gmail.com

Foto eherrero.jpg
  • Enric Herrero

Enric Herrero received his M.S. degree in Electric Engineering from the Universitat Politècnica de Catalunya (UPC) and the Royal Institute of Technology (KTH) in 2006. He also received his B.S. in Industrial Engineering from the Universitat Politècnica de Catalunya (UPC) in 2003. He joined the ARCO research group in 2006 where he is pursuing his PhD studies. His current research interests are memory hierarchy design for multicore architectures and low-power designs. Contact him at eherrero(at)ac.upc.edu

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  • Marc Pons

2000 – 2005: M.Sc., Telecommunications, from the Universitat Politecnica de Catalunya (Barcelona, Spain). 2006 – Present: Ph.D. Student at the Electronic Engineering Department in collaboration with the Intel Barcelona Research Center and the Computer Architecture Department. Working on Design for Manufacturability for Deep Sub-Micron CMOS technologies. Research focused on Regular Layouts to reduce the impact of Process Variations on Integrated Circuits. Contact him at pons(at)ac.upc.edu

Foto jlira.jpg
  • Javier Lira

Javier Lira received his M.S. degree in Computer Science from the Universitat Politècnica de Catalunya (UPC), in Barcelona, Spain in 2006.  He started his PhD with the ARCO research group in 2008. His research interests are focused on memory hierarchy designs on chip multiprocessors. Contact him at javier.lira(at)ac.upc.edu

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  • Marc Lupon

Marc Lupon received both B.S and M.S degrees in Computer Engineering from the Universitat Politècnica de Catalunya (Barcelona, Spain) in 2008. He joined the ARCO research group in the summer of 2007, where he is working in his PhD. His current research interests are in multicore architectures and parallel programming models, with special focus on Transactional Memory. Contact him at mlupon(at)ac.upc.edu

Foto rranjan.jpg
  • Rakesh Ranjan

Rakesh received his B.Tech in Computer Science and Engineering from Institute of Technology, BHU (India) in 2003. From 2003 to 2005 he was an Engineer with Samsung Electronics where he worked in the 3G Mobile Handset group. He started his PhD with the ARCO group in 2005 where he is doing research on compiler and microarchitecture techniques for Speculative Multithreaded Architectures. Contact him at rranjan(at)ac.upc.edu

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  • Govind S

Govind is currently a PhD student working jointly with Prof Antonio and Prof Jordi Tubella. He completed his Master of Science in Engineering from the Indian Institute of Science, Bangalore and his Bachelor of Engineering from the National Institute of Technology, Jaipur. His research interests are in network processor architecture and architecture for security systems. Contact him at govind(at)ac.upc.edu