Difference between revisions of "Main Page"

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On average, we have observed that mechanisms evaluated in this Msc thesis do not achieve a high performance potential.<br>We believe that this is mainly due to the low hit ratio achieved on NUCA caches. This issue lead us to feel that benchmarks, workloads, or most probably, executed regions do not represent a typical CMP scenario. For instance, benchmarks with better hit ratios provide higher benefits. In this way, next steps in this work are focused on solving this drawback which may be hiding higher benefits of the implemented mechanisms.
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= ARCO Research Group <br>  =
 
= ARCO Research Group <br>  =
  
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*[[People|People]]  
 
*[[People|People]]  
 
*[[Projects|Projects]]  
 
*[[Projects|Projects]]  
*[[Publications|Publications]]
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*[[Publications|Publications]]  
 
*[[Theses|Theses]]  
 
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*[[Contact|Contact]]
 
*[[Contact|Contact]]

Revision as of 16:31, 28 August 2008

On average, we have observed that mechanisms evaluated in this Msc thesis do not achieve a high performance potential.
We believe that this is mainly due to the low hit ratio achieved on NUCA caches. This issue lead us to feel that benchmarks, workloads, or most probably, executed regions do not represent a typical CMP scenario. For instance, benchmarks with better hit ratios provide higher benefits. In this way, next steps in this work are focused on solving this drawback which may be hiding higher benefits of the implemented mechanisms.

ARCO Research Group

The research group ARCO (Architectures and Compilers) at the Universitat Politècnica de Catalunya (UPC) in Barcelona, Catalonia (Spain-EU) is formed by members of the Department of Computer Architecture at UPC, members of the Intel-UPC Barcelona Research Center and members of the Computer Science Department at the Universitat Rovira Virgili (URV). The group is formed by professors, PhD students, and post-doc researchers. The research of the group focuses on microarchitectures and compilers for future processors, bearing in mind the underlying technology. The main goal is to increase performance, enhance reliability and reduce power dissipation of future processors.


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