Publications Old

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2006

  • O. Unsal, J. Tschanz, K. Bowman, V. De, X. Vera, A. González, O. Ergin, Impact of Parameter Variations on Circuits and Microarchitecture, in IEEE Micro, vol 26(6), Nov-Dec 2006


  • O. Ergin, O. Unsal, X. Vera, A. González, Exploiting Narrow Values for Soft Error Tolerance, in IEEE Computer Architecture Letters, vol 5(2), 2006

  • M. Monchiero, R. Canal, A. González, Design Space Exploration for Multicore Architectures: A Power/Performance/Thermal View, In Proceedings of the 20th International Conference on Supercomputing (ICS'06), Cairns (Australia), June 2006


  • J. Abella, A. González, Heterogeneous Way-Size Cache, In Proceedings of the 20th International Conference on Supercomputing (ICS'06), Cairns (Australia), June 2006


  • E. Quiñones, J.-M. Parcerisa and A. González, Selective Predicate Prediction for Out-of-Order Processors, In Proceedings of the 20th. International Conference on Supercomputing (ICS'06), pp. 46-54, Cairns (Australia), June 2006


  • D. Oro, R. Canal, A. González, J. E. Smith, Power/Performance/Thermal trade-offs in microarchitecture, Intel Academic Forum 2006 Dublin (Ireland), June 2006


  • M. Monchiero, R. Canal, A. González, Design Space Exploration for MulticoreArchitectures: A Power/Performance/Thermal View, Intel Academic Forum 2006 Dublin (Ireland), June 2006


  • Montserrat Vaqué, Anna Arola, Carles Aliagas and Gerard Pujadas. BDT: an easy-to-use front-end application for automation of massive docking tasks and complex docking strategies with AutoDock. In Oxford Journals of Bioinformatics, May 2006. online paper


  • J. Abella, A. González, SAMIE-LSQ: Set-Associative Multiple-Instruction Entry Load/Store Queue, In Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS'06), Rodhes (Greece), April 2006


  • X. Vera, J. Abella, O. Unsal, A. González, O. Ergin, Checker Cluster for Soft and Timing Error Detection and Recovery, In the 2nd Workshop on System Effects of Logic Soft Errors (SELSE'06), Urbana-Champaign (Illinois), April 2006


  • X. Vera, O. Unsal, A. González, X-Pipe: An Adaptive Resilient Microarchitecture for Parameter Variations, In 1st ASGI Workshop, held with ISCA-33


  • O. Unsal, O. Ergin, X. Vera, A. González, Empowering a Helper Cluster through Data-Width Aware Instruction Selection Policies, in  20th International Parallel & Distributed Processing Symposium (IPDPS06), April 2006


  • A. Settle, D.Connors, E. Gibert, A. González, A Dynamically Reconfigurable Cache for Multithreaded Processors, Journal of Embedded Computing, Volume 2 Issue 2, April 2006


  • E. Gibert, J. Abella, X. Vera, J. Sánchez, A. González, A Heterogeneous Multi-Module Data Cache for VLIW Processors, In the 5th Explicitly Parallel Instruction Computing Workshop (EPIC'06) held in conjunction with CGO'06, New York (New York), March 2006


  • E. Gibert, J. Sánchez and A. González, Compilation Techniques for a Word-Interleaved Cache Clustered VLIW Processor, in Concurrency and Computation: Practice and Experience, 18:1391-1411, 2006


2005

  • S. Bieschewski, J.-M. Parcerisa and A. González, Memory Bank Predictors, In Proceedings of the 2005 IEEE International Conference on Computer Design (ICCD-2005), pp. 666-668, October 2005


  • E. Gibert, J. Sánchez and A. González, Distributed Data Cache Designs for Clustered VLIW Processors, in IEEE Transactions on Computers, volume 54, number 10, pp. 1227-1241, October 2005


  • C.Molina, J.Tubella and A.González, Reducing Misspeculation Penalty in Trace Level Speculative Multithreaded Architectures, In Proceedings of the 6th International Symposium on High Performance Computing, (ISHPC'05) Nara City (Japan), September 2005. (Paper),(Slides)


  • X. Vera, J. Abella, J. Llosa, A. González, An Accurate Cost Model for Guiding Data Locality Transformations, In ACM Transactions on Programming Languages and Systems (TOPLAS), Volume 27, Issue 5, September 2005


  • E. Gibert, J. Abella, J. Sánchez, X. Vera, A. González, Variable-Based Multi-module Data Caches for Clustered VLIW Processors, In Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05), Saint Louis (Missouri), September 2005


  • T. Jones, M.F.P. O'Boyle, J. Abella, A. González, O. Ergin, Compiler Directed Early Register Release, In Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques (PACT'05), Saint Louis (Missouri), September 2005


  • R. Canal, A. González, J.E. Smith, Value Compresson for Efficient Computation, 2005 European Conference on Parallel Computing (Europar'05), Lisboa (Portugal); printed also in Lecture Notes in Computer Science v. 3648, pp. 519-529, August 2005


  • A. Aletà, J.M. Codina, A. González, D. Kaeli, Demystifying On-the-Fly Spill Code, In Proceedings of the Conference on Programming Language Design and Implementation (PLDI'05), June 2005


  • C. García, C. Madriles, J. Sánchez, P. Marcuello, A. González and D. Tullsen, Mitosis Compiler: An Infrastructure for Speculative Threading Based on Pre-Computation Slices, In Proceedings of the Conference on Programming Language Design and Implementation (PLDI´05), June 2005. (Paper)


  • J. Abella, A. González, Inherently Workload-Balanced Clustered Microarchitecture, In Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS'05), Denver (Colorado), April 2005


  • J. Abella, A. González, X. Vera, M.F.P. O'Boyle, IATAC: A Smart Predictor to Turn-off L2 Cache Lines, In ACM Transactions on Architecture and Code Optimization (TACO), March 2005


  • C.Molina, A.González and J.Tubella, Compiler Analysis for Trace Level Speculative Multithreaded Architectures, In Proceedings of the 9th Annual Workshop on Interaction between Compilers and Computer Architectures, (INTERACT´05), held in conjunction with the 11th International Symposium on High-Performance Computer Architecture (HPCA'05), San Francisco (USA), February 2005. (Paper),(Slides)


  • T. Jones, M.F.P. O'Boyle, J. Abella, A. González, Software Assisted Issue Queue Power Reduction, In Proceedings of the 11th International Symposium on High Performance Computer Architecture (HPCA'05), San Francisco (California), February 2005


  • J.-M. Parcerisa, J. Sahuquillo, A. González and J. Duato, On-Chip Interconnects and Instruction Steering Schemes for Clustered Microarchitectures, In IEEE Transactions on Parallel and Distributed Systems (TPDS), Volume 16, Issue 2, pp. 130-144, February 2005


2004

  • X. Vera, N. Bermudo, J. Llosa, A. González, A Fast and Accurate Framework to Analyze and Optimize Cache Memory Behavior, in ACM Transactions on Programming Languages and Systems (TOPLAS), 2004


  • J. Xue, X. Vera, Efficient and Accurate Analytical Modeling of Whole-Program Data Cache Behavior, in IEEE Transactions on Computers (TC), 2004


  • A. Aletà, J.M. Codina, A. González, D. Kaeli, Removing Communications in Clustered Microarchitectures Through Instruction Replication, in ACM Transactions on Architecture and Code Optimization (TACO), Volume 1, Issue 2 (June 2004), pages: 127 - 151

  • J. Abella, R. Canal, A. González, Power and Complexity Aware Microarchitectures, Poster at the 9th Intel EMEA Academic Forum, Barcelona (Spain), April 2004


  • J.-M. Parcerisa and A. González, Design of Clustered Superscalar Microarchitectures, Poster at the 9th. EMEA International Academic Forum, Barcelona (Spain), April 2004.


  • R. Canal, A. González, J.E. Smith, Software- Controlled Operand Gating, Proc. of the International Symposium on Code Generation and Optimization (CGO-2), Palo Alto (CA-USA), pp. 125-136, March 2004


  • J. Abella, A. González, Low-Complexity Distributed Issue Queue, In Proceedings of the 10th International Symposium on High Performance Computer Architecture (HPCA'04), Madrid (Spain), February 2004


2003

  • A. Aletà, J.M. Codina, A. González, D. Kaeli, Instruction Replication for Clustered Microarchitectures, in Proceedings of 36th International Symposium on Microarchitecture (MICRO36) , San Diego (CA), December 2003

  • E. Gibert, J. Sánchez and A. González, Flexible Compiler-Managed L0 Buffers for Clustered VLIW Processors, in Proceedings of 36th International Symposium on Microarchitecture (MICRO36) , pp. 315-325, Dec. 2003


  • J. Abella, A. González, Power-Aware Adaptive Issue Queue and Register File, In Proceedings of the International Conference on High Performance Computing (HiPC'03), Hyderabad (India), December 2003


  • X. Vera, B. Lisper, J. Xue, Data Caches in Multitasking Real-Time Systems, in 24th International Real-Time Systems Symposium (RTSS03), December 2003


  • J. Abella, A. González, Power Efficient Data Cache Designs, In Proceedings of the 21st International Conference in Computer Design (ICCD'03), San Jose (California), October 2003


  • J. Abella, A. González, On Reducing Register Pressure and Energy in Multiple-Banked Register Files, In Proceedings of the 21st International Conference in Computer Design (ICCD'03), San Jose (California), October 2003


  • J. Abella, R. Canal, A. González, Power- and Complexity-Aware Issue Queue Designs, IEEE Micro, Special Issue on Power- and Complexity-Aware Design, September-October 2003


  • Q. Huang, J. Xue, X. Vera, Code Tiling for Improving the Cache Performance of PDE Solvers, in 32nd International Conference on Parallel Processing (ICPP03), October 2003


  • X. Vera, J. Abella, A. González, J. Llosa, Optimizing Program Locality through CMEs and GAs, In Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques (PACT'03), New Orleans (Louisiana), September 2003


  • C.Aliagas, C.Molina, M.García, A.González and J.Tubella, Value Compression to Reduce Power in Data Caches, Lecture Notes in Computer Science, Springer-Verlag Heidelberg (ISSN 0302-9743), vol. 2790, pp. 616-622, August 2003. (Paper)


  • C.Molina, C.Aliagas, M.García, A.González and J.Tubella, Non Redundant Data Cache, In Proceedings of the International Symposium on Low Power Electronics and Design, (ISLPED'03), Seoul (Korea), August 2003. (Paper),(Slides)


  • C.Aliagas, C.Molina, M.García, A.González and J.Tubella, Value Compression to Reduce Power in Data Caches, In Proceedings of the International Conference on Parallel and Distributed Computing, (EURO-PAR'03), Klagenfurt (Austria), August 2003. (Paper),(Slides)


  • X. Vera, Björn Lisper, J. Xue, Data Cache Locking for Higher Program Predictability, in International Conference on Measurement and Modeling of Computer Systems (SIGMETRICS03), June 2003


  • E. Gibert, J. Sánchez and A. González, Local Scheduling Techniques for Memory Coherence in a Clustered VLIW Processor with a Distributed Data Cache, in Proceedings of 1st International Symposium on Code Generation and Optimization (CGO-1), pp. 193-203, March 2003


  • E. Gibert, J. Sánchez, A. González, Compilation Techniques for a Word-Interleaved Cache Clustered VLIW Processor, in Proceedings of 10th International Workshop on Compilers for Parallel Computers (CPC-2003), Amsterdam, The Netherlands, pp. 91-100, January 2003


2002

  • E. Gibert, J. Sánchez and A. González, Effective Instruction Scheduling Techniques for an Interleaved Cache Clustered VLIW Processor, in Proceedings of 35th International Symposium on Microarchitecture (MICRO35), pp. 123-133, Nov. 2002


  • X. Vera, J. Xue, Efficient Compile-Time Analysis of Cache Behaviour for Programs with IF Statements, in International Conference on Algorithms and Architectures for Parallel Processing, October 2002


  • A. Aletà, J.M. Codina, J. Sánchez, A. González and D. Kaeli, Exploiting Pseudo-schedules to Guide Data Dependence Graph Partitioning, in Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT'02), Charlottesville (VA), September 2002


  • J.-M. Parcerisa, J. Sahuquillo, A. González and J. Duato, Efficient Interconnects for Clustered Microarchitectures, In Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT-2002),  pp. 291-300, Charlottesville (VA), September 2002


  • C.Molina, A.González and J.Tubella, Trace Level Speculative Multithreaded Architecture, In Proceedings of the International Conference on Computer Design, (ICCD'02), Freiburg (Germany), September 2002. (Paper),(Slides)


  • J. Abella, A. González, J. Llosa, X. Vera, Near-Optimal Loop Tiling by means of Cache Miss Equations and Genetic Algorithms, In Proceedings of the Workshop on Compiler/Runtime Techniques for Parallel Computing (CRTPC'02) held in conjunction with ICPP'02, Vancouver (British Columbia, Canada), August 2002 (also published in XIII Jornadas de Paralelismo)


  •  X. Vera, A. González, J. Llosa, Near-Optimal Padding for Removing Conflict Misses, in 15th International Workshop on Languages and Compilers for Parallel Computing (LCPC02), July 2002


  • E. Gibert, J. Sánchez and A. González, An Interleaved Cache Clustered VLIW Processor, in Proceedings of International Conference on Supercomputing (ICS'02), pp. 210-219, June 2002


  • X. Vera, J. Xue, Let’s Study Whole-Program Cache Behaviour Analytically, in 8th International Symposium on High-Performance Computer Architecture (HPCA-8), February 2002


2001

  • A. Aletà, J.M. Codina, J. Sánchez and A. González, Graph-Partitioning Based Instruction Scheduling for Clustered Processors, in Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture (MICRO'34), Austin (TX), December 2001


  • J.-M. Parcerisa and A. González, Improving Latency Tolerance of Multithreading through Decoupling, IEEE Transactions on Computers, Volume 50, Issue 10, pp. 1084-1094, October 2001


  • R. Canal, A. González, Reducing the Complexity of the Issue Logic, Proc. of the International Conference on Supercomputing (ICS-01). Sorrento (Italy), June 16-21, 2001


  • R. Canal, J.-M. Parcerisa, A. González, Dynamic Code Partitioning for Clustered Architectures, International Journal of Parallel Programming vol. 29 n. 1 pp. 59-79, Kluwer Academic/Plenum Publishers, February 2001


2000

  • R. Canal, A. González, J.E. Smith, Very Low Power Pipelines using Significance Compression, Proc. of the International Symposium on Microarchitecture (MICRO-33), Monterey (CA-USA), pp. 181-190, Dec. 2000


  • J.-M. Parcerisa and A. González, Reducing Wire Delay Penalty through Value Prediction, In Proceedings of the 33rd. International Symposium on Microarchitecture (MICRO-33), pp. 317-326, Monterey, CA (USA), December 2000


  • X. Vera, J. Llosa, A. González, N. Bermudo, A Fast and Accurate Approach to Analyze Cache Memory Behavior, in 6th International Euro-Par Conference (EuroPar 2000), August/September 2000


  • J. Abella, S.A.A. Touati, A. Anderson, C. Ciuraneta, J.M. Codina, M. Dai, C. Eisenbeis, G. Fursin, A. González, J. Llosa, M. O'Boyle, A. Randrianatoavina, J. Sánchez, O. Temam, X. Vera, G. Watts, The MHAOTEU Toolset, In proceedings of the Agent-Based Simulation, Planning and Control of the 16th IMACS World Congress 2000, on Scientific Computation, Applied Mathematics and Simulation (IMACS'00), Lausanne (Switzerland), August 2000


  • R. Canal, A. González, A Low-Complexity Issue Logic, Proc. of the International Conference on Supercomputing (ICS-00). Santa Fe (USA). May 8-11, 2000


  • N. Bermudo, X. Vera, A. González, J. Llosa, An Efficient Solver for Cache Miss Equations, in IEEE International Symposium on Performance Analysis of Software and Systems (ISPASS00) , April 2000


  • N. Bermudo, X. Vera, A. González, J. Llosa, Optimizing Cache Miss Equations Polyhedra, in 4th Annual Workshop on Interaction between Compilers and Computer Architectures (INTERACT4), January 2000

  • R. Canal, J.-M. Parcerisa, A. González, Dynamic Cluster Assigment Mechanisms, In Proceedings of the 6th. International Symposium on High-Performance Computer Architecture (HPCA-6), pp. 133-142, Toulouse (France), January 10-12, 2000 (Best student paper)


  • X. Vera, J. Llosa, A. González, C. Ciuraneta, A Fast Implementation of Cache Miss Equations, in 8th Workshop on Compilers for Parallel Computers, January 2000


Before 2000

  • R. Canal, J.M. Parcerisa and A. González, A Cost-Effective Clustered Architecture, Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques (PACT-99), pp.160-168, New Port Beach, CA (USA), Oct. 12-16, 1999


  • A.González, J.Tubella and C.Molina, Trace Level Reuse, In Proceedings of the International Conference on Parallel Processign, (ICPP'99), Tokyo (Japan), September 1999. (Paper),(Slides)


  • C.Molina, A.González and J.Tubella, Dynamic Removal of Redundant Computations, In Proceedings of International Conference on Supercomputing, (ICS'99), Rhodes (Greece), June 1999. (Paper),(Slides)


  • C.Molina, A.González and J.Tubella, Reducing Memory Traffic Via Redundant Store Instructions, Lecture Notes in Computer Sciences, Springer-Verlag Heidelberg (ISSN 0302-9743), vol. 1593, pp. 1246-1249, April 1999. (Paper)


  • C.Molina, A.González and J.Tubella, Reducing Memory Traffic Via Redundant Store Instructions, In Proceedings of the International Conference on High Performance Computing and Networking, (HPCN'99), Amsterdam (The Netherlands), April 1999. (Paper)


  • J.-M. Parcerisa and A. González, The Synergy of Multithreading and Access/Execute Decoupling, In Proceedings of the 5th. International Symposium on High-Performance Computer Architecture (HPCA-5), pp. 59-63, January 1999

  • J.-M. Parcerisa and A. González, The Latency Hiding Effectiveness of Decoupled Access/Execute Processors, In Proceedings of the 24th. Euromicro Conference, (EUROMICRO-98), pp 293-300, Vasteras (Sweden), August 1998

  • A. González, M. Valero, N. Topham and J.-M. Parcerisa, Eliminating Cache Conflict Misses Through XOR-Based Placement Functions, In Proceedings of the 1997 International Conference on Supercomputing (ICS'97), pp. 76-83, July 1997


  • Antonio González, Carlos Aliagas and Mateo Valero. A Data Cache with Multiple Caching Strategies Tuned to Different Types of Locality. (ICS'95),Barcelona, June 1995. (Paper)


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