Projects

Domain-Specific Architectures for Energy-Efficient Computing SystemsI I(2024-2028)

We are entering a new era in computing, characterized by the integration of many diverse computing devices into our daily lives. These systems will encompass a range of functions akin to human cognitive tasks, such as comprehending our surroundings (e.g., vision and language processing), learning from data and experiences, and making proactive decisions and autonomous actions (e.g., self-driving cars). This era marks the dawn of ubiquitous intelligent computing.

However, these computing systems will necessitate significant advancements in energy efficiency, as they will execute complex tasks under stringent power constraints. While chip manufacturing process technology has been instrumental in improving energy efficiency over generations, advances in dimension scaling have recently slowed down, leading many experts to believe that dimension scaling may soon reach a halt. In this context, disruptive innovations in architecture will become pivotal in enhancing energy efficiency and driving innovation. This project focuses on developing these disruptive architecture innovations.

Our approach to designing these novel architectures will be grounded in three key pillars: simplicity, minimal data movement, and hardware-software specialization. This specialization will lead to the development of domain-specific architectures. In this project, we will concentrate on two domains that we believe will be highly popular and impactful in the future: cognitive computing and graphics.

Cognitive computing encompasses a broad range of artificial intelligence techniques, including machine learning, that enable computers to interact and think like humans (perception, reasoning, learning, decision-making, etc.). Graphics are the primary means used by most applications to display data to users. Animated graphics applications, such as games and movies, demand exceptionally high-quality graphics, low latency, and often operate under tight power constraints (e.g., mobile devices). The ultimate objective of this research project is to design novel domain-specific architectures that provide exceptional user experiences in these two domains.

Domain-Specific Architectures for Energy-Efficient Computing Systems (2020-2025)

We are on the verge of transitioning to a new era in computing, characterized by an abundance of very different computing devices integrated in most systems that surround us in our daily lives. Besides, these computing systems will include a rich set of functions that are similar to human cognitive tasks, such as the ability to comprehend our surroundings (e.g., vision and language processing), learn from data and experiences, and proactively take decisions and autonomous actions (e.g., self-driving cars). This will be the era of ubiquitous intelligent computing.

These computing systems will require dramatic improvements in energy-efficiency since they will perform very complex tasks under tightly constrained power budgets. Traditional approaches to improve energy-efficiency are running out of gas, and disruptive innovations from architecture are going to be a main driving force for energy-efficiency in the future. These disruptive architecture innovations are the main focus on this project.

Our approach for designing these novel architectures will rely on four main pillars: simplicity, minimal data movement and specialization of the both hardware and software. This specialization will give rise to different domain-specific architectures. In this project we will focus on two particular domains that we believe will be among the among the most popular in the forthcoming future: cognitive computing and graphics.

Cognitive computing is a broad area that includes machine learning and other artificial intelligence techniques that will allow computers to interact and think like humans (perception, reasoning, learning, decision making etc.). Graphics are the common way used by most applications to display data to users. Applications such as games and movies demand for extremely high-quality graphics, and in many cases (e.g., mobile devices) have very tight power constraints. The ultimate goal of this project is to devise novel domain-specific architectures that provide rich user experiences in these two areas.

CoCoUnit: An Energy-Efficient Processing Unit for Cognitive Computing (2019-2025)

There is a fast-growing interest in extending the capabilities of computing systems to perform human-like tasks in an intelligent way. These technologies are usually referred to as cognitive computing. We envision a next revolution in computing in the forthcoming years that will be driven by deploying many “intelligent” devices around us in all kind of environments (work, entertainment, transportation, health care, etc.) backed up by “intelligent” servers in the cloud. These cognitive computing systems will provide new user experiences by delivering new services or improving the operational efficiency of existing ones, and altogether will enrich our lives and our economy.

A key characteristic of cognitive computing systems will be their capability to process in real time large amounts of data coming from audio and vision devices, and other type of sensors. This will demand a very high computing power but at the same time an extremely low energy consumption. This very challenging energy-efficiency requirement is a sine qua non to success not only for mobile and wearable systems, where power dissipation and cost budgets are very low, but also for large data centers where energy consumption is a main component of the total cost of ownership.

Current processor architectures (including general-purpose cores and GPUs) are not a good fit for this type of systems since they keep the same basic organization as early computers, which were mainly optimized for “number crunching”. CoCoUnit will take a disruptive direction by investigating unconventional architectures that can offer orders of magnitude better efficiency in terms of performance per energy and cost for cognitive computing tasks. The ultimate goal of this project is to devise a novel processing unit that will be integrated with the existing units of a processor (general purpose cores and GPUs) and altogether will be able to deliver cognitive computing user experiences with extremely high energy-efficiency.

This project is funded by the European Research Council through the ERC Advanced Grants program.

Intelligent, Ubiquitous and Energy-Efficient Computing Systems (2016-2020)

The ultimate goal of this project is to devise novel platforms that provide rich user experiences in the areas of cognitive computing and computational intelligence in mobile devices such as smartphones or wearable devices. This project investigates novel unconventional architectures that can offer orders of magnitude better efficiency in terms of performance per energy, and at the same time important improvements in raw performance. These platforms will rely on various types of units specialized for different application domains. Special focus is paid to graphics processors and brain-inspired architectures (e.g. hardware neural networks) due to their potential to exploit high degrees of parallelism and their energy efficiency for this type of applications. Extensions to existing architectures combined with novel accelerators will be explored. We also investigate the use of resilient architectures that can allow computing systems to operate at very low supply voltage levels in order to optimize their energy consumption while not compromising their reliability by providing adequate fault tolerance solutions.

Microarquitecture and Compilers for Future Processors III (2014-2016)

The main objective of this project as for the researchers of the ARCO group is the research in the design of future microprocessors, taking into account the determining factors of future technology, both for high performance processors and for commodity electronics. Fundamentally, two factors have determined the increased performance in processors: on one hand the technological advances in microprocessor manufacturing and, on the other hand, the use of new and more efficient microarchitectural and compiler techniques. All these improvements bring a number of challenges that are now considered as key in designing the processors for this upcoming decade: the limited instruction-level parallelism, the interconnection network delays, high power consumption, heat dissipation, system relibility and security. In this project we are going to address the influence of these issues in the research of future processors. Specifically, we will address six areas that we consider fundamental:

1. The efficient design of circuits in the presence of unexpected changes in its operating parameters
2. The efficient design of graphic processors oriented to mobile devices
3. The efficient implementation of virtual machines with low complexity but high computing power
4. The characterization and acceleration of emerging applications
5. The design of new heterogeneous multiprocessor architectures that optimize the use of the different processors depending on the types of application being executed
6. The study of new techniques in the design of the memory hierarchy and interconnection networks to tolerate the increasing gap between the speeds of the various components of the computer.

Microarquitecture and Compilers for Future Processors II (2010-2014)

The main objective of this project as for the researchers of the ARCO group is the research in the design of future microprocessors, taking into account the determining factors of future technology, both for high performance processors and for commodity electronics. Fundamentally, two factors have determined the increased performance in processors: on one hand the technological advances in microprocessor manufacturing and, on the other hand, the use of new and more efficient microarchitectural and compiler techniques. All these improvements bring a number of challenges that are now considered as key in designing the processors for this upcoming decade: the limited instruction-level parallelism, the interconnection network delays, high power consumption, heat dissipation, system relibility and security. In this project we are going to address the influence of these issues in the research of future processors. Specifically, we will focus on five areas which we consider to be fundamental:

1. The study of new techniques in the memory hierarchy design to tolerate the increasing gap between processor and memory speeds
2. The efficient circuit design in the face of unexpected variations of their working parameters
3. The implementation of efficient virtual machines of low complexity but high level computing
4. The implementation of intrusion detection systems to assure a high computer security level
5. Characterization and acceleration of emerging applications
6. The design of novel multithreaded processors to exploit thread-level parallelism

Microarquitecture and Compilers for Future Processors (2006-2010)

The main objective in this project is to research the design of next decade processors considering the requirements of the technology which is estimated to be feasible for the next years. Till recently, processor performance was mainly determined by two factors: technological advances in microprocessor manufacturing and the use of new and more efficient microarchitectural and compiler techniques. Now, new challenges are approached, for instance: high power consumption, heat dissipation, wire delays, design complexity, and the limited instruction-level parallelism. In this project we are going to address the influence of these issues in the research of future processors. Specifically, we will focus on seven areas which we consider to be fundamental:

1. The reduction in power consumption and better approaches for heat dissipation
2. The exploitation of thread-level speculative parallelism
3. The design of clustered microarchitectures
4. The efficient implementation of ISA extensions for out-of-order processors
5. The efficient implementation of co-designed virtual machines;
6. The study of new techniques in the register file and cache memory design to tolerate the increasing gap between processor and memory speeds;
7. The efficient circuit design in the face of unexpected variations of their working parameters.

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