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Alex Aletà finished a Masters degree in Mathematics in the Universitat Politècnica de Catalunya (UPC) in june 2000. In October 2000 I started the PhD in Computer Architecture with Professor Antonio González in the same university. Since then, I have been working on instruction scheduling and code optimization for clustered VLIW architectures. In particular, I have been working on Modulo Scheduling. We have proposed graph partitioning techniques to address cluster assignment and we have optimized scheduling and spill code schemes. I will be graduating in December 2008. '''''Contact him at aaleta(at)ac.upc.edu''''' | Alex Aletà finished a Masters degree in Mathematics in the Universitat Politècnica de Catalunya (UPC) in june 2000. In October 2000 I started the PhD in Computer Architecture with Professor Antonio González in the same university. Since then, I have been working on instruction scheduling and code optimization for clustered VLIW architectures. In particular, I have been working on Modulo Scheduling. We have proposed graph partitioning techniques to address cluster assignment and we have optimized scheduling and spill code schemes. I will be graduating in December 2008. '''''Contact him at aaleta(at)ac.upc.edu''''' | ||
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*'''Nivard Aymerich''' | |||
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Nivard Aymerich is currently working as a research scientist at Intel Labs Barcelona, where he is developing automated tools for early and accurate reliability estimation of computing systems in an international team environment. He holds BSc and MSc (2009) degrees in Industrial + Telecommunication engineering double-degree program from Universitat Politècnica de Catalunya (UPC), Barcelona, Spain. In 2013, he completed his PhD in Electronics Engineering from Universitat Politècnica de Catalunya (UPC) under the advisory of Prof. Antonio Rubio. His research interests include on Fault-tolerant Circuits, Nanoscale Reliable Computing and Degradation-Aware Architectures based on Redundancy. He has participated in two European FP7 projects, published 5 research articles in international journals and several papers in prestigious conferences. '''''Contact him at nivard.aymerich(at)intel.com''''' | |||
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2000 - 2004 : Bachelor of Technology in Computer Science and Engineering from Institute of Technology, Banaras Hindu University, India. 2004 - 2005 : Software Engineer at Globallogic, India. 2006 - 2012 : PhD Student. Worked with Enric Gibert and Jesus Sanchez. Research Interests include code optimizations for energy-efficient architectures, and co-desinged virtual machines. Currently at Oracle. | 2000 - 2004 : Bachelor of Technology in Computer Science and Engineering from Institute of Technology, Banaras Hindu University, India. 2004 - 2005 : Software Engineer at Globallogic, India. 2006 - 2012 : PhD Student. Worked with Enric Gibert and Jesus Sanchez. Research Interests include code optimizations for energy-efficient architectures, and co-desinged virtual machines. Currently at Oracle. | ||
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*'''Qiong Cai''' | |||
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Qiong Cai was born in Shanghai, China on 15 December, 1976. He went to Australia in 1997 for his bachelor study, and graduated from University of Wollongong in 2000 with Bachelor of Computer Science and Bachelor of Mathematics. He continued his study in University of New South Wales as an honours student supervised by Professor Jingling Xue and graduated with Bachelor of Computer Science (the first class honours) in 2001. He pursued his PHD research in compilers under the supervision of Professor Jingling Xue in 2002 and received the degree in 2006. The title of thesis is profile-guided redundancy elimination. Since July of 2005 he has been working as a Senior Research Scientist in the Intel Barcelona Research Center. His research interests include low power microarchitecture and programmable accelerator. '''''Contact him at qiongx.cai(at)intel.com''''' | |||
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Revision as of 09:51, 23 June 2017
Professors
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Antonio González received his Ph.D. degree from the Universitat Politècnica de Catalunya (UPC), in Barcelona, Spain, in 1989. He joined the faculty of the Computer Architecture Department of UPC in 1986 and became a Full Professor in 2002. He was the founding director of the Intel Barcelona Research Center from 2002 to 2014. Contact him at antonio(at)ac.upc.edu |
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Carles Aliagas recieved his M.S degree from the the Universitat Politècnica de Catalunya (UPC), in Barcelona, Spain. He joined the Computer Science and Mathematics Department of Rovira i Virgili University in Tarragona where he is currently working as an associate professor. His areas of interest are computer architecture, operating systems and parallelism. His research is focused on memory hierarchies for microprocessors. Contact him at carles.aliagas(at)urv.net |
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Josep-Llorenç Cruz received his M.S. degree from the Universitat Politècnica de Catalunya (UPC), in Barcelona, Catalonia, Spain in 1996. He joined the faculty of the Computer Architecture Department at the Universitat Politècnica de Catalunya (UPC) in 2001 where he is currently a lecturer. His research interests include processor microarchitecture, instruction level parallelism, memory hierarchies for microprocessors, education and ethics in computer science. Contact him at cruz(at)ac.upc.edu |
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Joan-Manuel Parcerisa received his M.S. and Ph.D. degrees in Computer Science from the Universitat Politècnica de Catalunya (UPC), in Barcelona, Spain, in 1993 and 2004 respectively. Since 1994 he is a professor at the Computer Architecture Department in the Universitat Politècnica de Catalunya. His current research topics include clustered microarchitectures, multithreading, and low power GPUs for mobile devices. Contact him at jmanel(at)ac.upc.edu |
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Jordi Tubella received his M.S. and Ph.D. degrees in Computer Science from the Universitat Politècnica de Catalunya (UPC), in Barcelona, Spain, in 1986 and 1996 respectively. Since 1988 he is a professor at the Computer Architecture Department in the Universitat Politècnica de Catalunya. His current research is oriented to network processors. Contact him at jordit(at)ac.upc.edu |
External Collaborators from Industry
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Nivard Aymerich is currently working as a research scientist at Intel Labs Barcelona, where he is developing automated tools for early and accurate reliability estimation of computing systems in an international team environment. He holds BSc and MSc (2009) degrees in Industrial + Telecommunication engineering double-degree program from Universitat Politècnica de Catalunya (UPC), Barcelona, Spain. In 2013, he completed his PhD in Electronics Engineering from Universitat Politècnica de Catalunya (UPC) under the advisory of Prof. Antonio Rubio. His research interests include on Fault-tolerant Circuits, Nanoscale Reliable Computing and Degradation-Aware Architectures based on Redundancy. He has participated in two European FP7 projects, published 5 research articles in international journals and several papers in prestigious conferences. Contact him at nivard.aymerich(at)intel.com |
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Qiong Cai was born in Shanghai, China on 15 December, 1976. He went to Australia in 1997 for his bachelor study, and graduated from University of Wollongong in 2000 with Bachelor of Computer Science and Bachelor of Mathematics. He continued his study in University of New South Wales as an honours student supervised by Professor Jingling Xue and graduated with Bachelor of Computer Science (the first class honours) in 2001. He pursued his PHD research in compilers under the supervision of Professor Jingling Xue in 2002 and received the degree in 2006. The title of thesis is profile-guided redundancy elimination. Since July of 2005 he has been working as a Senior Research Scientist in the Intel Barcelona Research Center. His research interests include low power microarchitecture and programmable accelerator. Contact him at qiongx.cai(at)intel.com
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Josep M. Codina received his M.S. and Ph.D in computer science from the Universitat Politècnica de Catalunya. He joined Intel in October 2004 as a senior research scientist at Intel Barcelona Research Center. His research interests include computer architecture and compilers, with special emphasis on instruction and thread level parallelism, code generation and dynamic binary optimization. Contact him at josep.m.codina(at)intel.com |
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Ayose Falcón received his BS (1998) and MS (2000) degrees in Computer Science from the University of Las Palmas de Gran Canaria. In 2005, he completed his PhD in Computer Science from the Universitat Politècnica de Catalunya (UPC) under the advisory of Prof. Mateo Valero and Dr. Alex Ramirez. His PhD research focused on fetch unit optimization, especially branch prediction and instruction prefetching, for superscalar and SMT processors. During his PhD years, Ayose was a summer intern and then a consultant at Intel Microprocessor Research Labs, and worked as teach assistant at UPC for one year. From 2004 to 2009, he was a (Senior) Research Scientist at HP Labs in Barcelona. His research interests included simulation and virtualization technologies, disciplines in which he published several papers and disclosed 7 patents. Since January 2010 he is a Senior Research Scientist at Intel Barcelona Research Center. His research focuses on new memory hierarchy designs for future Intel processors. Contact him at ayose.falcon(at)intel.com |
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Enric Gibert received the bachelor and M.S. degrees in Computer Engineering from Enginyeria i Arquitectura La Salle (Universitat Ramon Llull) in 1995 and 1998 respectively. From 1996 to 2000, he was a professor of the Departament d'Informàtica of Enginyeria i Arquitectura La Salle, teaching on topics related to digital systems, operating systems and information systems. In September 2000 he joined the Departament d'Arquitectura de Computadors (UPC) to pursue a PhD degree under the supervision of Antonio González and Jesús Sánchez and graduated in November 2005. In March 2005, he joined the Intel Barcelona Research Center (IBRC) as a senior research scientist. His main research interests are on the area of processor microarchitecture and compilation techniques, with special emphasis on memory hierarchy, dynamic binary optimization, and instruction and thread level parallelism. Contact him at enric.gibert(at)intel.com |
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Enric Herrero received his M.S. degree in Electric Engineering from the Universitat Politècnica de Catalunya (UPC) and the Royal Institute of Technology (KTH) in 2006. He also received his B.S. in Industrial Engineering from the Universitat Politècnica de Catalunya (UPC) in 2003. He joined the ARCO research group in 2006 to pursue a PhD degree, which he obtained in 2011. In March 2011, he joined the Intel Barcelona Research Center (IBRC) as a senior research scientist. His current research interests are reliability, memory hierarchy design for multicore architectures and low-power designs. Contact him at enric.herrero(at)intel.com |
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Juan Fernández received his M.S. and Ph.D. degrees from the University of Murcia, Spain, in 1997 and 2005 respectively. He worked as a graduate research assistant at Los Alamos National Laboratory from 2001 to 2003, as a postdoc at Pacific Northwest National Laboratory in 2006, and as assistant and associate professor at the Computer Engineering Department of the Universidad de Murcia in the periods in between from 1997 until 2011. He currently works as a senior research scientist at Intel Barcelona Research Center. His research interests include high-performance computing, parallel programming and multicore processor microarchitecture.Contact him at juan.fernandez(at)intel.com
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Fernando Latorre received the MS degree in Computer Engineering from the Centro Politécnico Superior of the Zaragoza university at Zaragoza, Spain, in 2001. He joined the Departament d'Arquitectura de Computadors (Universitat Politècnica de Catalunya) and got his PhD in 2009. Since March 2003, he is a research scientist at the Intel Barcelona Research Center. His main research interests are in multi-core architectures, thread-level parallelism and dynamic binary optimization.Contact him at fernando.latorre(at)intel.com |
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Javier Lira completed Computer Engineering from Universitat Politècnica de Catalunya (UPC) in 2006. From 2004 to the end of 2007, he was working for Hewlett‐Packard, first as student and then as software engineer. He started his PhD with the ARCO group in January 2008 where he did research on memory management for multi‐core architectures, focusing on Non‐Uniform Cache Architectures (NUCA), under the supervision of Prof. Carlos Molina (URV) and Prof. Antonio González (Intel and UPC). He graduated in November 2011, and is currently working at Intel Barcelona Research Center. Contact him at javierx.lira(at)intel.com |
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Marc Lupon received his PhD in Computer Architecture from the Universitat Politècnica de Catalunya (Barcelona, Spain) in 2011. Before that, he obtained both B.S and M.S degrees in Computer Engineering from UPC in 2008. His current research interests are in multicore architectures and parallel programming models, with special focus on Transactional Memory and co-designed HW/SW processors. He is working at Intel Barcelona Research Center as a Research Scientist since spring of 2011. Contact him at marc.lupon(at)intel.com |
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Carlos Madriles received the MS degree in Computer Engineering from the Universitat Politècnica de Catalunya (UPC) at Barcelona, Spain, in 2002. He joined the Dept. of Computer Architecture of the UPC-Barcelona in 2001 as a research assistant. Since May 2002, he is a research scientist of the Intel Barcelona Research Center. He is currently doing the PhD in the UPC-Barcelona on the area of speculative thread-level parallelism. His current research interests are in multi-core architectures and compilation techniques, with special emphasis in speculative multithreading and transactional memory. Contact him at carlos.madriles.gimeno(at)intel.com |
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Alejandro Martínez received the MS degree in computer science and the PhD degree from the University of Castilla-La Mancha in 2003 and 2007, respectively. He is currently with the Intel Barcelona Research Center. His research interests include high-performance interconnections, quality of service, high-performance computing, and processor microarchitecture. Contact him at alejandrox.martinez(at)intel.com |
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Raúl Martínez received the MS degree in computer science from the University of Castilla-La Mancha in 2003 and the PhD degree from the University of Castilla-La Mancha in 2007. He is currently a researcher in the Intel Barcelona Research Center. His research interests include high performance local area networks, quality of service (QoS), design of high-performance switches, and processor microarchitecture. Contact him at raulm(at)ac.upc.edu |
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Daniel Ortega received his B.S and M.S from the University of Las Palmas de Gran Canaria, and his Ph.D. from the Department of Computer Architecture at Universitat Politècnica de Catalunya. He joined HP Labs in August 2003 and worked there under the mentorship of Paolo Faraboschi until December 2009, when he joined the Intel Barcelona Research Center. Contact him at daniel.ortega(at)intel.com |
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Serkan Ozdemir received his BSc degree in Microelectronics from Sabanci University (Istanbul, Turkey) in July 2004 and later his PhD degree in Computer Engineering from Northwestern University (Evanston, IL, USA) in December 2009. The title of his PhD thesis was "Mitigating the Effects of Process Variations through Microarchitectural Techniques" which he completed under the advisory of Prof. Gokhan Memik. Serkan is currently working as a senior research scientist at Intel-Labs Barcelona since March 2010, where he is conducting research on new memory hierarchy designs for future Intel processors. Contact him at serkan(dot)ozdemir(at)intel(dot)com |
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Demos Pavlou received his B.Sc.degree in Computer Science from the University of Cyprus in 2008. He joined the ARCO research group in September 2008 where he is working towards his PhD degree. Since April 2011 he is a senior research scientist at Intel Barcelona Research Center. His main research interests are Virtual Machines, Dynamic Binary Optimizers and processor microarchitecture. Contact him at demos(dot)pavlou(at)intel(dot)com |
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Frederico Pratas is currently a Postdoc researcher scientist at Intel Labs Barcelona. He holds a PhD (2012) and an MSc (2007) in Electrical and Computer Engineering from Instituto Superior Técnico, Universidade Técnica de Lisboa, Portugal. He has developed his PhD research work at the Signal Processing Systems group at INESC-ID, Lisboa, and his MSc research work at the Computer Engineering group, TUDelft, The Netherlands. His research interests lie in the fields of Computer Architectures and Microarchitectures, Reconfigurable Computing and Parallel Computing. Contact him at frederico.c.pratas(at)intel.com
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Tanausú Ramírez is a research scientist at Intel Labs Barcelona since December 2009. Previously, he obtained the B.S. and M.S. in Computer Science from University of Las Palmas de Gran Canaria, Spain. He received the PhD. degree in April 2010 from the "Universitat Politecnica de Catalunya", Barcelona. His current research interests include architectural aspects of future processors, hardware reliability, and variations-aware microarchitectures. Contact him at tanausu(dot)ramirez(at)intel(dot)com |
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Georgios Tournavitis is currently a senior research scientist at Intel Labs Barcelona. He earned a PhD from the Institute for Computing Systems Architecture, University of Edinburgh. He also holds an Engineering Diploma and an MSc in Computer Engineering from the University of Patras, Greece. His research interests lie in the areas of compilation and programming languages for parallel architectures. More specifically, he is interested in compiler-based and runtime techniques that enable compilers to extract high-level parallelization skeletons from sequential applications. Contact him at georgios.tournavitis(at)intel.com
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Ferad Zyulkyarov earned his MSc and PhD degrees at the Universitat Politècnica de Catalunya in 2008 and 2011, respectively. His PhD research explored the concepts of programming, debugging, profiling and optimizing transactional memory applications. The key contributions were AtomicQuake, new debugging principles and profiling techniques for transactional applications. In May 2011, Ferad joined Intel Labs Barcelona as a research scientist and his current research studies are related to persistent programing with non-volatile memory. Contact him at feradx.zyulkyarov(at)intel.com
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Postdoctoral Researchers
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Alejandro Valero received the PhD degree in Computer Engineering from the Universitat Politècnica de València (Spain) in 2013. He was a visiting researcher at Northeastern University (USA) and the University of Cambridge (UK) in 2013-14 and 2014-15, respectively. In 2012, his research was recognized with the Intel Doctoral Student Honor Programme Award. His thesis focused on the design of hybrid cache memories, high-performance cache replacement algorithms, and refresh mechanisms for on-chip eDRAM caches. He joined the ARCO group in December 2015 and his current research focuses on architectures for cognitive computing. Contact him at avalero(at)ac.upc.edu |
PhD Students
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Jose Maria Arnau received B.S degree in Computer Engineering from the University Jaume I (Castellón, Spain) in 2008. He joined the ARCO research group in 2010 and he received M.S degree in Computer Architecture, Networks and Systems from the Universitat Politècnica de Catalunya (Barcelona, Spain) in 2011. He is currently pursuing PhD, his research is focused on the design of energy efficient mobile GPUs for smartphones. Contact him at jarnau(at)ac.upc.edu |
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Aleksandar Brankovic received his Diploma in Electrical Engineering from University of Belgrade (Serbia) and the M.S. degree in Embedded Systems Design from Faculty of Informatics (University of Lugano - Switzerland) in 2007 and 2009 respectively. He joined the ARCO group in September 2009 and his current research is focused on co-designed virtual machine evaluation. Contact him at abrankov(at)ac.upc.edu |
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Enrique de Lucas received B.S. degree in Computer Science in 2010 and M.S. degree in Computer Engineering in 2011 both from Complutense University of Madrid (Spain). In 2011 he worked as Research Assistant in ArTecs research group developing a methodology for automatic design with HDL over FPGAs. During 2012 he was intern at Intel Barcelona Research Center (IBRC) focusing on processor microarchitecture. He joined ARCO research group by February 2013 and is currently pursuing PhD. His research is focused on the design of energy efficient mobile GPUs for smartphones. Contact him at edelucas(at)ac.upc.edu |
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Gem Dot Artigas received B.S degree in Computer Engineering from Universitat Autònoma de Barcelona (UAB) in 2011. He joined the ARCO research group in 2012 and he received M.S degree in Computer Architecture, Networks and Systems from the Universitat Politècnica de Catalunya (UPC) in 2012. He is currently pursuing PhD and his research is focused on Hardware/Software Co-designed Virtual Machines along with Alejandro Martínez and Antonio González. Contact him at gdot(at)ac.upc.edu |
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Sudhanshu Shekhar Jha received BE in Computer Science Engineering from Birla Institute of Technology, Mesra in 2006. Received Masters in Embedded Systems Design from Advanced Learning and Research Institute (ALaRI), affiliated with ETH Zurich, Politecnico di Milano and Universita della Svizzera Italiana in Switzerland in 2011. Joined ARCO in 2011 and current research is focused towards many-core architecture.Contact him at to.sjha(at)gmail.com
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Emilio Martínez received B.S degree in Computer Engineering and the M.S. degree in Computer Architecture from the Complutense University of Madrid (Madrid, Spain) in 2007 and 2009 respectively. He joined the ARCO group in January 2014. He is currently pursuing PhD, his research is focused on the design of efficient memory architecture for high-performance computers.Contact him at emiliom(at)ac.upc.edu |
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Rakesh received his masters degree in Microelectronics from Birla Institute of Technology and Sciences (BITS), Pilani, India and his bachelors degree in Electronics and Communication Engineering from Kuruksherta University, Kuruksherta, India in 2008 and 2005. He joined ARCO group at Universitat Politècnica de Catalunya (Barcelona, Spain) in September 2009 as a PhD student. Currently, he is working on optimizing SIMD execution in Hardware/Software Co-designed Virtual Machines along with Alejandro Martínez and Antonio González.Contact him at rkumar(at)ac.upc.edu |
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2000 – 2005: M.Sc., Telecommunications, from the Universitat Politecnica de Catalunya (Barcelona, Spain). 2006 – Present: Ph.D. Student at the Electronic Engineering Department in collaboration with the Intel Barcelona Research Center and the Computer Architecture Department. Working on Design for Manufacturability for Deep Sub-Micron CMOS technologies. Research focused on Regular Layouts to reduce the impact of Process Variations on Integrated Circuits. Contact him at pons(at)ac.upc.edu
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Albert Segura received his BS degree in Computer Engineering in 2014, and his MS degree in MIRI: High Performance Computing in 2016, both from Universitat Politècnica de Catalunya (UPC - BarcelonaTech). He joined ARCO research group by September 2015 and is currently pursuing a PhD, his research focuses on the area of Cognitive Computing on GPU Architectures. Contact him at asegura(at)ac.upc.edu.
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Hamid received his M.Sc in Computer Architecture from University of Tehran (Tehran, Iran) in july 2014. His thesis was about energy-efficient resource allocation among mobile devices considering both intra- and inter-devices simultaneously. He joined ARCO research group in November 2014 to pursue a PhD degree. Hamid works under supervision of Dr. Jose Maria Arnau, Prof. Jordi Tubella and Prof. Antonio Gonzalez. Contact him at htabani(at)ac.upc.edu.
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Gaurang was born on November 21st, 1985 in India. He completed his Bachelors in Technology with a major in Electronics and Communications from Nirma University, India in 2007. He pursued his Masters in Embedded Systems Design from Advanced Learning and Research Institute (ALaRI), affiliated with ETH, Zurich, Politecnico di Milano and Universita della Svizzera Italiana in Switzerland in 2009. Currently, he is pursuing a Ph.D with the ARCO group in collaboration with Intel Barcelona Research Center under the supervision of Xavier Vera and Antonio Gonzalez. He is currently working on reliable and variation-aware microarchitecture design, focusing on the issues related to soft-errors in CMOS memories. Contact him at gaurang(at)ac.upc.edu |
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Darko Zivanovic received his BSc and MSc degrees from the Faculty of Electrical Engineering, University of Belgrade in Serbia, in 2008 and 2010 respectively. During his Master he joined the Institute Mihajlo Pupin in Belgrade, where he worked for 2 years as Embedded System Developer. He joined ARCO group in November 2011 and his current research is focused on Java execution on HW/SW Co-designed Virtual Machines. Contact him at dzivanov(at)ac.upc.edu |
Ex-Members
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Alex Aletà finished a Masters degree in Mathematics in the Universitat Politècnica de Catalunya (UPC) in june 2000. In October 2000 I started the PhD in Computer Architecture with Professor Antonio González in the same university. Since then, I have been working on instruction scheduling and code optimization for clustered VLIW architectures. In particular, I have been working on Modulo Scheduling. We have proposed graph partitioning techniques to address cluster assignment and we have optimized scheduling and spill code schemes. I will be graduating in December 2008. Contact him at aaleta(at)ac.upc.edu | |
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Nivard Aymerich is currently working as a research scientist at Intel Labs Barcelona, where he is developing automated tools for early and accurate reliability estimation of computing systems in an international team environment. He holds BSc and MSc (2009) degrees in Industrial + Telecommunication engineering double-degree program from Universitat Politècnica de Catalunya (UPC), Barcelona, Spain. In 2013, he completed his PhD in Electronics Engineering from Universitat Politècnica de Catalunya (UPC) under the advisory of Prof. Antonio Rubio. His research interests include on Fault-tolerant Circuits, Nanoscale Reliable Computing and Degradation-Aware Architectures based on Redundancy. He has participated in two European FP7 projects, published 5 research articles in international journals and several papers in prestigious conferences. Contact him at nivard.aymerich(at)intel.com | |
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2000 - 2004 : Bachelor of Technology in Computer Science and Engineering from Institute of Technology, Banaras Hindu University, India. 2004 - 2005 : Software Engineer at Globallogic, India. 2006 - 2012 : PhD Student. Worked with Enric Gibert and Jesus Sanchez. Research Interests include code optimizations for energy-efficient architectures, and co-desinged virtual machines. Currently at Oracle. | |
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Qiong Cai was born in Shanghai, China on 15 December, 1976. He went to Australia in 1997 for his bachelor study, and graduated from University of Wollongong in 2000 with Bachelor of Computer Science and Bachelor of Mathematics. He continued his study in University of New South Wales as an honours student supervised by Professor Jingling Xue and graduated with Bachelor of Computer Science (the first class honours) in 2001. He pursued his PHD research in compilers under the supervision of Professor Jingling Xue in 2002 and received the degree in 2006. The title of thesis is profile-guided redundancy elimination. Since July of 2005 he has been working as a Senior Research Scientist in the Intel Barcelona Research Center. His research interests include low power microarchitecture and programmable accelerator. Contact him at qiongx.cai(at)intel.com | |
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Ramon Canal received his M.S. and Ph.D. degrees from the Universitat Politècnica de Catalunya (UPC), in Barcelona, Catalonia, EU. He joined the faculty of the Computer Architecture Department of UPC in 2003 where he is currently an associate professor. He finished his M.S. in the University of Bath (UK), worked at Sun Microsystems in 2000, and was a Fulbright visiting scholar at Harvard University in the 2006/2007 school year. His research focuses mostly on power and thermal aware architectures, as well as reliability. He is currently the Associate Dean of Postgraduate Studies at the Barcelona School of Informatics (UPC). Contact him at rcanal(at)ac.upc.edu | |
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José Cano received the M.S. and Ph.D. degrees in Computer Science from the Universitat Politècnica de València, Valencia, Spain, in 2004 and 2012, respectively. He was a member with the Networking Research Group (between September 2005 and January 2012) and also with the Parallel Architectures Group (between December 2009 and January 2012) at the Department of Computer Engineering, Universitat Politècnica de València, Valencia, Spain. He joined the ARCO Research Group in March 2012, where he was a postdoctoral researcher with special emphasis on microarchitecture and HW/SW co-designed processors. Moreover, Multiprocessor Systems-on-Chip and Networks-on-Chip. Currently at the University of Edinburgh. | |
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Javier Carretero received the MS degree in Computer Engineering from the Universitat Politècnica de Catalunya (UPC) at Barcelona, Spain, in 2005. From 2006 to 2014, he was a research scientist at the Intel Barcelona Research Center. He received his PhD degree from the UPC in 2015. His main research interests include processor microarchitecture, hardware reliability, and lighteight on-line testing. | |
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Abhishek received his B.Tech in Computer Science and Engineering from Institute of Technology, BHU (India) in 2003. From 2003 to 2006 he was working with Philips Electronics India. He started his PhD with the ARCO group in 2006 where he worked with Prof. Antonio González and Dr. Josep Maria Codina. | |
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Zoran Jakšić received MSc degree from “University of Belgrade, Faculty of Electrical Engineering” and BSc degree from the “University of Montenegro, Faculty of Electrical Engineering” in 2010 and 2006. After graduating at “University of Montenegro” he joined “Institute Mihailo Pupin, Belgrade Serbia”, where he worked for 3 years as FPGA design engineer. He was PhD student at ARCO since March 2011. His research interest includes: FinFET technology, Variation – Aware computer architectures and hardware reliability. Intel Doctoral Student Programme Honoree 2014, he graduated in 2015. Contact him at zjaksic(at)ac.upc.edu | |
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Shrikanth received his Bachelor of Engineering in Electronics and Communication Engineering from Anna University in 2008 . He has been with ARCO since September 2008. Prior to joining ARCO , he worked as a Part-Time research trainee at Waran Research Foundation where his major focus was Design for Testability techniques for Heterogeneous Cores. His current research interests are Variation-Aware architectures and Hardware Reliability. Currently at EPFL. | |
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Christos Kotselidis was a senior research scientist at Intel Barcelona Research Center until 2012. He received his MSc and PhD degrees from the University of Manchester, in 2010, after completing his BSc in Applied Informatics at the University of Macedonia, Thessaloniki. His research interests include virtual machines, transactional memory, garbage collection and programming languages. Currently at Oracle. | |
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Associate Professor in Computer Architecture at Rovira i Virgili University of Tarragona, Spain. In 1996, he received a M.Sc. in Computer Engineering from the Universitat Politècnica de Catalunya (UPC), Barcelona, Spain. He also obtained the PhD degree in Computer Sciences from de Computer Architecture Department at the Universitat Politècnica de Catalunya, in 2005. His research was focused on multithreading architectures and data value reuse for superscalar processors. He is currently working on Chip Multiprocessors. Contact him at carlos.molina(at)urv.net
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Matteo Monchiero joined Intel Labs in April 2010 in the Intel Barcelona Research Center (IBRC) where he is currently working on reliability, testing, and debuggability for future Intel processors. Previously, he was a researcher at HP Labs in Palo Alto within the Exascale Computing Lab. His research interests include system architecture, processor architecture, and virtualization technologies. He received his PhD degree from the Politecnico di Milano, Italy, in 2007. You can access Matteo Monchiero’s personal webpage at http://themonchier.net. Currently at Intel Santa Clara. | |
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Sofia Pediaditaki received her Ph.D. in Computer Science from the University of Edinburgh. Her thesis focuses on the design of interference-aware adaptive spectrum management mechanims for wireless networks using unlicensed frequency bands. She received her M.Sc also from the University of Edinburgh and her bachelor degree from the Computer Science department at the the University of Crete. After joining Intel Barcelona Research Center in October 2011, her research is focusing on the development of novel techniques that will improve the energy efficiency of future multi-core systems. Currently at Intel Santa Clara. | |
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Manish received his Bachelor of Technology in Computer Engineering from National Institute of Technology, Kurukshetra in 2011. He joined ARCO group in October 2011. His PhD is on Sub-Threshold and Near-Threshold architectures focusing on SRAM memories. He graduated in 2016. Contact him at mrana(at)ac.upc.edu
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Rakesh received his B.Tech in Computer Science and Engineering from Indian Institute of Technology, BHU (India) (formerly ITBHU) in 2003. From 2003 to 2005 he was an Engineer with Samsung Electronics where he worked in the 3G Mobile Handset group. He started his PhD with the ARCO group in 2005 and defended his thesis in 2010 in the area of Compiler and Microarchitecture techniques for Speculative Multithreaded Architectures. Currently at Intel Santa Clara. | |
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Govind was a PhD student working jointly with Prof Antonio and Prof Jordi Tubella. He completed his Master of Science in Engineering from the Indian Institute of Science, Bangalore and his Bachelor of Engineering from the National Institute of Technology, Jaipur. His research interests are in network processor architecture and architecture for security systems. Contact him at govind(at)ac.upc.edu
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Xavier Vera received the M.S. degree in Computer Science in 2000 from Universitat Politecnica de Catalunya (UPC) at Barcelona (Spain). In July 2000, Xavier continued his studies in Sweden advised by Björn Lisper. He obtained his PhD from Mälardalens Högskola at Västerås (Sweden) in January, 2004. The title of the thesis was Cache and Compiler Interaction (how to analyze, optimize and time cache behavior, in collaboration with professor Jingling Xue from UNSW, Sydney (Australia), where Xavier spent 1.5 years. Xavier has been with Intel since February 2004, participating in research in the area of reliable and variations-aware microarchitectures. Contact him at xavier.vera(at)intel.com | |
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Polychronis Xekalakis was a senior research scientist at Intel-Labs Barcelona until 2012. He received his Ph.D. degree in Informatics from the University of Edinburgh in 2009. He received his Diploma in Electrical and Computer Engineering from the University of Patras in 2005. His research interests include co-designed virtual machines, speculative multithreading, and architectural techniques for low power. Currently at Intel Santa Clara.
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