Theses: Difference between revisions
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*Ramon Canal, '''Power- and Performance- Aware Architectures''', PhD. Thesis, Universitat Politècnica de Catalunya, Advisors: Antonio González and James E. Smith. June 2004.([http://personals.ac.upc.edu/rcanal/pdf/PowerAndPerformanceAwareArchitectures.pdf Document])([http://personals.ac.upc.edu/rcanal/pdf/pres-thesis.pdf slides])<br> | *Ramon Canal, '''Power- and Performance- Aware Architectures''', PhD. Thesis, Universitat Politècnica de Catalunya, Advisors: Antonio González and James E. Smith. June 2004.([http://personals.ac.upc.edu/rcanal/pdf/PowerAndPerformanceAwareArchitectures.pdf Document])([http://personals.ac.upc.edu/rcanal/pdf/pres-thesis.pdf slides])<br> | ||
*Joan-Manuel Parcerisa, '''Design of Clustered Superscalar Microarchitectures''', PhD. Thesis, Universitat Politècnica de Catalunya, Advisor: Antonio González. June 2004. ([http://personals.ac.upc.edu/jmanel/papers/parcerisa-phdthesis.pdf Document])<br> | *Joan-Manuel Parcerisa, '''Design of Clustered Superscalar Microarchitectures''', PhD. Thesis, Universitat Politècnica de Catalunya, Advisor: Antonio González. June 2004. ([http://personals.ac.upc.edu/jmanel/papers/parcerisa-phdthesis.pdf Document])<br> | ||
Revision as of 17:18, 22 February 2012
Master
- Jorge Martínez, DRAM-based on-chip cache architectures , Msc Thesis, Universitat Politècnica de Catalunya, September 2010.
- Shrikanth Ganapathy, Effect of Spatio-Temporal Variations on Memory Systems, Msc Thesis, Universitat Politècnica de Catalunya, July 2009.
- Javier Lira, Data Replacement Policy on Non-Uniform Cache Architectures for Chip Multiprocessors, Msc Thesis, Universitat Politècnica de Catalunya, September 2008.
- Marc Lupon, Hardware Approaches for Transactional Memory, Msc Thesis/PFC, Universitat Politècnica de Catalunya, June 2008. (Document)
- Enric Herrero, ArchitecturalLevel Power Simulator of the Memory Hierarchy of Chip Multiprocessors, Msc Thesis, Universitat Politècnica de Catalunya, June 2007.
Ph.D
- Marc Lupon,Architectural Support for High-Performing Hardware Transactional Memory Systems, Ph.D Thesis, Universitat Politècnica de Catalunya, December 2011. (Document),(Slides)
- Javier Lira, Managing Dynamic Non-Uniform Cache Architectures, Ph.D Thesis, Universitat Politècnica de Catalunya, November 2011. (Document),(Slides)
- Enric Herrero, Adaptive Memory Hierarchies for Next Generation Tiled Microarchitectures, Ph.D Thesis, Universitat Politècnica de Catalunya, July 2011. (Document),(Slides)
- Rakesh Ranjan, Speeding Up Sequential Applications on Multicore Platforms, Ph.D Thesis, Univesitat Politécnica de Catalunya, November 2010.
- Carlos Molina, Microarchitectural Techniques to Exploit Repetitive Computations and Values, Ph.D Thesis, Universitat Politècnica de Catalunya, December 2005. (Document),(Slides)
- Enric Gibert, Clustered Data Cache Designs for VLIW Processors, PhD Thesis, Universitat Politècnica de Catalunya, November 2005. (Document),(Slides)
- Jaume Abella, Adaptive and Low-Complexity Microarchitectures for Power Reduction, Ph.D Thesis, Universitat Politècnica de Catalunya, July 2005. (Document)
- Ramon Canal, Power- and Performance- Aware Architectures, PhD. Thesis, Universitat Politècnica de Catalunya, Advisors: Antonio González and James E. Smith. June 2004.(Document)(slides)
- Joan-Manuel Parcerisa, Design of Clustered Superscalar Microarchitectures, PhD. Thesis, Universitat Politècnica de Catalunya, Advisor: Antonio González. June 2004. (Document)
