Theses: Difference between revisions
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== Master == | == Master == | ||
* | *Jorge Martínez, <span class="Apple-style-span" style="font-weight: bold;"></span>'''DRAM-based on-chip cache architectures''' , Msc Thesis, Universitat Politècnica de Catalunya, September 2010.<br> | ||
<br> | <br> | ||
*Shrikanth Ganapathy, '''Effect of Spatio-Temporal Variations on Memory Systems''', Msc Thesis, Universitat Politècnica de Catalunya, July 2009. <br> | |||
<br> | |||
*Javier Lira, '''Data Replacement Policy on Non-Uniform Cache Architectures for Chip Multiprocessors''', Msc Thesis, Universitat Politècnica de Catalunya, September 2008.<br> | *Javier Lira, '''Data Replacement Policy on Non-Uniform Cache Architectures for Chip Multiprocessors''', Msc Thesis, Universitat Politècnica de Catalunya, September 2008.<br> | ||
*Marc Lupon, '''Hardware Approaches for Transactional Memory''', Msc Thesis/PFC, Universitat Politècnica de Catalunya, June 2008. [[Media:Mlupon_msc.pdf|(Document)]] | *Marc Lupon, '''Hardware Approaches for Transactional Memory''', Msc Thesis/PFC, Universitat Politècnica de Catalunya, June 2008. [[Media:Mlupon_msc.pdf|(Document)]] | ||
*Enric Herrero, '''ArchitecturalLevel Power Simulator of the Memory Hierarchy of Chip Multiprocessors''', Msc Thesis, Universitat Politècnica de Catalunya, June 2007.<br> | |||
<br> | <br> | ||
Revision as of 08:11, 4 October 2010
Master
- Jorge Martínez, DRAM-based on-chip cache architectures , Msc Thesis, Universitat Politècnica de Catalunya, September 2010.
- Shrikanth Ganapathy, Effect of Spatio-Temporal Variations on Memory Systems, Msc Thesis, Universitat Politècnica de Catalunya, July 2009.
- Javier Lira, Data Replacement Policy on Non-Uniform Cache Architectures for Chip Multiprocessors, Msc Thesis, Universitat Politècnica de Catalunya, September 2008.
- Marc Lupon, Hardware Approaches for Transactional Memory, Msc Thesis/PFC, Universitat Politècnica de Catalunya, June 2008. (Document)
- Enric Herrero, ArchitecturalLevel Power Simulator of the Memory Hierarchy of Chip Multiprocessors, Msc Thesis, Universitat Politècnica de Catalunya, June 2007.
Ph.D
- Carlos Molina, Microarchitectural Techniques to Exploit Repetitive Computations and Values, Ph.D Thesis, Universitat Politècnica de Catalunya, December 2005. (Document),(Slides)
- Enric Gibert, Clustered Data Cache Designs for VLIW Processors, PhD Thesis, Universitat Politècnica de Catalunya, November 2005. (Document),(Slides)
- Jaume Abella, Adaptive and Low-Complexity Microarchitectures for Power Reduction, Ph.D Thesis, Universitat Politècnica de Catalunya, July 2005. (Document)
