Theses

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Master 

  • Albert Segura, Characterization of Speech Recognition Systems on GPU Architectures, Msc Thesis, Universitat Politècnica de Catalunya, July 2016. (Document)


  • Martí Anglada, Soft Error Rate Analysis in Combinational Logic, Msc Thesis, Universitat Politècnica de Catalunya, July 2015. (Document)


  • Marc Riera, Analysis of Soft Error Rates for future technologies, Msc Thesis, Universitat Politècnica de Catalunya, July 2015. (Document)


  • Sicong Zhuang, Improving the Robustness of the Register File, Msc Thesis, Universitat Politècnica de Catalunya, September 2014.


  • Álvaro Martínez, A Quantitative Evaluation of State-of-art Memory Technologies, Msc Thesis, Universitat Politècnica de Catalunya, September 2012.


  • Manish Rana, Analyzing stability Concerns in the presence of variations in Subthreshold SRAM, Msc Thesis, Universitat Politècnica de Catalunya, June 2012.


  • José María Arnau, High Performance, Ultra-Low Power Streaming Systems, Msc Thesis, Universitat Politècnica de Catalunya, September 2011. (Document)


  • Jorge Martínez, DRAM-based on-chip cache architectures , Msc Thesis, Universitat Politècnica de Catalunya, September 2010.


  • Shrikanth Ganapathy, Effect of Spatio-Temporal Variations on Memory Systems, Msc Thesis, Universitat Politècnica de Catalunya, July 2009.


  • Javier Lira, Data Replacement Policy on Non-Uniform Cache Architectures for Chip Multiprocessors, Msc Thesis, Universitat Politècnica de Catalunya, September 2008.


  • Marc Lupon, Hardware Approaches for Transactional Memory, Msc Thesis/PFC, Universitat Politècnica de Catalunya, June 2008. (Document)


  • Enric Herrero, Architectural Level Power Simulator of the Memory Hierarchy of Chip Multiprocessors, Msc Thesis, Universitat Politècnica de Catalunya, June 2007.


Ph.D 

  • Martí Torrents, Improving Prefetching Mechanisms for Tiled CMP Platforms, Ph.D Thesis, Universitat Politècnica de Catalunya, December 2016. (Document),(Slides)


  • José María Arnau, Energy-Efficient Mobile GPU Systems, Ph.D Thesis, Universitat Politècnica de Catalunya, April 2015.


  • Aleksandar Brankovic, Performance Simulation Methodologies for Hardware/Software Co-Designed Processors, Ph.D Thesis, Universitat Politècnica de Catalunya, March 2015.


  • Rakesh Kumar, Optimizing SIMD Execution in Hardware/Software Co-Designed Processors, Ph.D Thesis, Universitat Politècnica de Catalunya, July 2014.


  • Shrikanth Ganapathy, Reliability in the Face of Variability in Nanometer Embedded Memories, Ph.D Thesis, Universitat Politècnica de Catalunya, April 2014.


  • Stefan Bieschewski, Design of a Distributed Memory Unit for Clustered Microarchitectures, Ph.D Thesis, Universitat Politècnica de Catalunya, June 2013.


  • Govind Sreekarshenoy, Architecture Support for Intrusion Detection Systems, Ph.D Thesis, Universitat Politècnica de Catalunya, Octubre 2012.


  • Carlos Madriles, Mitosis Based Speculative Multithreaded Architectures, Ph.D Thesis, Universitat Politècnica de Catalunya, July 2012.(Document)


  • Marc Pons, Layout Regularity for Design and Manufacturability, Ph.D Thesis, Universitat Politècnica de Catalunya, July 2012.


  • Abhishek Deb, HW/SW Mechanisms for Instruction Fusion, Issue and Commit in Modern u-Processors, Ph.D Thesis, Universitat Politècnica de Catalunya, May 2012.


  • Indu Bhagat, Code Optimizations For Narrow Bitwidth Architectures, Ph.D Thesis, Universitat Politècnica de Catalunya, February 2012.


  • Marc Lupon,Architectural Support for High-Performing Hardware Transactional Memory Systems, Ph.D Thesis, Universitat Politècnica de Catalunya, December 2011. (Document),(Slides)


  • Javier Lira, Managing Dynamic Non-Uniform Cache Architectures, Ph.D Thesis, Universitat Politècnica de Catalunya, November 2011. (Document),(Slides)


  • Enric Herrero, Adaptive Memory Hierarchies for Next Generation Tiled Microarchitectures, Ph.D Thesis, Universitat Politècnica de Catalunya, July 2011. (Document),(Slides)


  • Rakesh Ranjan, Speeding Up Sequential Applications on Multicore Platforms, Ph.D Thesis, Univesitat Politécnica de Catalunya, November 2010.


  • Alexandre Aleta, Instruction Scheduling for Clustered Processors based on Graph Techniques, Ph.D Thesis, Univesitat Politécnica de Catalunya, Octubre 2009.


  • Fernando Latorre, Clustered Multithreaded Processors, Ph.D Thesis, Univesitat Politécnica de Catalunya, June 2009.


  • Eduardo Quiñones, Predicated execution and register windows for out-of-order processors, Ph.D Thesis, Univesitat Politécnica de Catalunya, November 2008.


  • Jose Maria Codina, Single-Phase Instruction Scheduling for Clustered Architectures, Ph.D Thesis, Univesitat Politécnica de Catalunya, April 2008.


  • Pedro Chaparro, Thermal Aware Microarchitectures, Ph.D Thesis, Univesitat Politécnica de Catalunya, February 2008.


  • Carlos Molina, Microarchitectural Techniques to Exploit Repetitive Computations and Values, Ph.D Thesis, Universitat Politècnica de Catalunya, December 2005. (Document),(Slides)


  • Enric Gibert, Clustered Data Cache Designs for VLIW Processors, PhD Thesis, Universitat Politècnica de Catalunya, November 2005. (Document),(Slides)


  • Jaume Abella, Adaptive and Low-Complexity Microarchitectures for Power Reduction, Ph.D Thesis, Universitat Politècnica de Catalunya, July 2005. (Document)


  • Ramon Canal, Power- and Performance- Aware Architectures, PhD. Thesis, Universitat Politècnica de Catalunya, Advisors: Antonio González and James E. Smith. June 2004.(Document)(slides)


  • Joan-Manuel Parcerisa, Design of Clustered Superscalar Microarchitectures, PhD. Thesis, Universitat Politècnica de Catalunya, Advisor: Antonio González. June 2004. (Document)