Publications

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2018

  • Hamid Tabani, Jose-Maria Arnau, Jordi Tubella, Antonio Gonzalez, A Novel Register Renaming for Out-of-Order Processors, High Performance Computer Architecture (HPCA), 24th International Conference on, Vienna, Austria.

2017

  • Hamid Tabani, Jose-Maria Arnau, Jordi Tubella, Antonio Gonzalez, An Ultra Low-power Hardware Accelerator for Acoustic Scoring in Speech Recognition, Parallel Architecture and Compilation Techniques (PACT), 26th International Conference on, Portland, USA.

  • Hamid Tabani, Jose-Maria Arnau, Jordi Tubella, Antonio Gonzalez, Performance Analysis and Optimization of Automatic Speech Recognition, IEEE Transactions on Multi-Scale Computing Systems (TMSCS).

  • C.Aliagas, M.Torrents, R.Martínez, C.Molina and A.González, Prioritization of Prefetching Traffic into Multicore Networks, In Proceedings of the 4th URV Doctoral Workshop in Computer Science and Mathematics (DCSM 2017), Tarragona, (Spain), November 2017. (Paper),(Slides)

  • Reza Yazdani, Albert Segura, Jose-Maria Arnau, and Antonio Gonzalez, Low-Power Automatic Speech Recognition Through a Mobile GPU and a Viterbi Accelerator, IEEE Micro ( Volume: 37, Issue: 1, Jan.-Feb 2017 ), April 2017. (Paper)

2016

  • Reza Yazdani, Albert Segura, Jose-Maria Arnau, and Antonio Gonzalez, An Ultra Low-Power Hardware Accelerator for Automatic Speech Recognition, IEEE/ACM International Symposium on Microarchitecture (MICRO'49), December 2016. (Paper),(Slides)

  • R.Santos, J.Orozco, M.Micheletto, S.Ochoa, R.Meseguer, P.Millan and C. Molina, Scheduling Real-Time Traffic in Underwater Acoustic Wireless Sensor Networks, 10th International Conference on Ubiquitous Computing and Ambient Intelligence (UCAMI'16), Las Palmas de Gran Canaria (Spain), November 2016. (Paper),(Slides)

  • R.Santos, J.Orozco, M.Micheletto, S.Ochoa, R.Meseguer, P.Millan and C. Molina, Real-Time Traffic in Underwater Acoustic Wireless Sensor Networks, 13rd URV Doctoral Workshop in Computer Science and Mathematics (DCSM'16), Tarragona, (Spain), November 2016. (Paper)

  • M.Anglada, R.Canal, J.L.Aragón and A.Gonzalez, MASkIt: Soft error rate estimation for combinational circuits, IEEE International Conference on Computer Design (ICCD-34), October 2016 (Paper)

  • M. Riera, R. Canal, J. Abella and A. Gonzalez, A detailed methodology to compute Soft Error Rates in advanced technologies, Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, 2016 (Paper)

  • S.Bieschewski, J.-M.Parcerisa and A.Gonzalez, An Energy-Efficient Memory Unit for Clustered Microarchitectures, IEEE Transactions on Computers, Vol. 65, no. 8, August 2016 (Paper)

  • M.Torrents, R.Martínez, C. Molina, Facing Prefetching Challenges in Distributed Shared Memories, The Journal of Supercomputing (JSC'16), February 2016. (Paper)

  • R. Kumar, A. Martínez, and A. González. Assisting Static Compiler Vectorization with a Speculative Dynamic Vectorizer in an HW/SW Codesigned Environment. In ACM Transactions on Computer Systems (TOCS), Volume 33 Issue 4, Article 12 (January 2016). (Paper)

2015

  • E. de Lucas, P. Marcuello, J.-M. Parcerisa and A. Gonzalez, Ultra-Low Power Render-Based Collision Detection for CPU/GPU Systems, In Proceedings of the 48th International Symposium on Microarchitecture (MICRO 2015), Honolulu, HI (USA), December 2015. (Paper), (Slides)

  • P. Millán, C. Molina, R.Meseguer, Improving Prediction in the Routing Layer of Wireless Networks Through Social Behaviour, In Proceedings of the 2nd URV Doctoral Workshop in Computer Science and Mathematics (DCSM 2015), Tarragona, (Spain), November 2015. (Paper),(Slides)

  • P. Millán, C. Molina, R.Meseguer, E.Medina, D.Vega, B.Braem, C.Blondia, Time Series Analysis to Predict Link Quality of Wireless Community Networks, The International Journal of Computer and Telecommunications Networking, October 2015. (Paper)

  • P.Millán, C. Molina, E.Dimogerontakis, L.Navarro, R.Meseguer, B.Braem and C.Blondia, Tracking and Predicting End-to-End Quality in Wireless Community Networks, In Proceedings of the 4th International Workshop on Community Networks and Bottom-up-Broadband (CNBuB 2015), In conjunction with the 3rd International Conference on Future Internet of Things and Cloud (FiCloud 2015), Rome, (Italy), August 2015. (Paper),(Slides)

  • M.Torrents, R.Martínez, C. Molina, An Accurate and Detailed Prefetching Simulation Framework for gem5 , The Second gem5 User Workshop (GEM5'15), held in conjuction with the 42nd International Symposium on Computer Architecture (ISCA'15), Portland, (USA), June 2015. (Paper),(Slides)

  • M.Torrents, R.Martínez, C. Molina, Prefetching Challenges in Distributed Memories for CMPs, In Proceedings of the International Conference on Computational Science (ICCS'15), Reykjavík, (Iceland), June 2015. (Paper),(Slides)

  • M.Torrents, R.Martínez, C. Molina, Improving the Prefetching Performance Through Code Region Profiling, In Proceedings of the 2nd International BSC Doctoral Symposium (BSC'15), Barcelona, (Spain), May 2015. (Paper),(Slides)

  • E. Amat, A. Colomarde, F. Moll, R. Canal, A. Rubio, Feasibility of the embedded DRAM cells implementation with FinFET devices, IEEE Transactions on Computers (in press, preprint available) 2015

  • E. Amat, A. Colomarde, F. Moll, R. Canal, A. Rubio, Variability Influence on FinFET-based On-chip Memory Data Paths, Journal of Low Power Electronics v. 11, n. 2, June 2015

2014

  • S. Ganapathy, G. Karakonstantis, A. Burg and R. Canal, Variability - Aware Design Space Exploration Of Embedded Memories, IEEE 28th Convention of Electrical and Electronics Engineers in Israel, Eilat (Israel), December 2014

  • M. Rana, R. Canal, REEM: Failure/Non-Failure region Estimation method for SRAM yield analysis, IEEE International Conference on Computer Design (ICCD-32), Seoul (Korea), October 2014

  • S. Ganapathy, R. Canal, A. Gonzalez and A. Rubio, iRMW: A Low-Cost Technique to Reduce NBTI-Dependent Parametric Failures in L1 Caches (Best paper nomenee), IEEE International Conference on Computer Design (ICCD-32), Seoul (Korea), October 2014

  • R. Kumar, A. Martínez, and A. González. Efficient power gating of SIMD accelerators through dynamic selective devectorization in a HW/SW codesigned environment. In ACM Transactions on Architecture and Code Optimization (TACO), Volume 11 Issue 3, October 2014. (paper)

  • E. Amat, C.G. Almudéver, N. Aymerich, R. Canal, A. Rubio, Strategies to enhance the 3T1D-DRAM cell variability robustness beyond 22nm, Microelectronics Journal v. 45, n. 10, pp. 1342–1347, October 2014

  • P. Millán, C. Molina, R.Meseguer, E.Medina, D.Vega, B.Braem, C.Blondia, Tracking and Predicting Link Quality in Wireless Community Networks, In Proceedings of the 3rd International Workshop on Community Networks and Bottom-up-Broadband (CNBuB 2014), In conjunction with the 10th IEEE International Conference on Wireless and Mobile Computing, Networking and Communications (WIMOB'14), Larnaca, (Cyprus), October 2014. (Paper),(Slides)

  • P. Millán, C. Molina, R. Meseguer, S. F. Ochoa, R. Santos, Using a History-Based Approach to Predict Topology Control Information in Mobile Ad Hoc Networks, In Proceedings of the 7th International Conference on Internet and Distributed Computing Systems (IDCS'14), Calabria, (Italy), September 2014. (Paper),(Slides)

  • E. Amat, A. Calomarde, R. Canal, A. Rubio, "Variability impact on on-chip memory data paths. IEEE 5th European Workshop on CMOS Variability (VARI'14), Palma de Mallorca (Spain), September-October 2014

  • E. Amat, C.G. Almudéver, N. Aymerich, R. Canal, A. Rubio, Suitability of the FinFET 3T1D cell beyond 10nm, IEEE Transactions on Nanotechnology v.13, n.5, pp.926-932, September 2014

  • G. Upasani, X. Vera and A. Gonzalez. Framework for Economical Error Recovery in Embedded Cores. In Proceedings of the International On-Line Testing Symposium (IOLTS'14), July 2014.

  • M.Torrents, R.Martínez, C. Molina, Network Aware Performance Evaluation of Prefetching Techniques in CMPs, Journal of Simulation Modelling Practice and Theory, Volume 45, June 2014. (Paper)

  • G. Upasani, X. Vera and A. Gonzalez. Avoiding Core's DUE & SDC via Acoustic Wave Detectors and Tailored Error Containment and Recovery. In Proceedings of the International Symposium on Computer Architecture (ISCA'14), June 2014.

  • J.M. Arnau, J.M. Parcerisa and P. Xekalakis. Eliminating Redundant Fragment Shader Executions on a Mobile GPU via Hardware Memoization. In Proceedings of the International Symposium on Computer Architecture (ISCA'14), June 2014.

  • A. Brankovic, K. Stavrou, E. Gibert, and A. González. Accurate Off-Line Phase Classification for HW/SW Co-Designed Processors. In Proceedings of the ACM International Conference on Computing Frontiers (CF '14). Cagliari, Italy, May 2014.

  • M. Lupon, E. Gibert, G. Magklis, S. Samudrala, R. Martinez, K. Stavrou, D. R. Ditzel, Speculative Hardware/Software Co-designed FP Multiply-Add Fusion, In Proceedings of the XIX Intl Conf on Architecture Support for Programming Languages and Operating Systems (ASPLOS'14), Salt Lake City (USA), March 2014.

  • E. Amat, A. Calomarde, C.G. Almudever, N. Aymerich, R. Canal, A. Rubio, Impact of FinFET and III-V/Ge technology on logic and memory cell behavior, IEEE Transactions on Device and Materials Reliability v.14, n. 1, pp. 344 - 350, March 2014

  • M. Rana, R. Canal, SSFB: A Highly-Efficient and Scalable Simulation Reduction Technique for SRAM Yield Analysis, IEEE Design, Automation and Test in Europe Conference (DATE’14), Dresden (Germany), March 2014

  • Z. Jakšić, R. Canal, DRAM-based Coherent Caches and how to take advantage of the coherence protocol to reduce the refresh power, IEEE Design, Automation and Test in Europe Conference (DATE’14), Dresden (Germany), March 2014

  • S.Ganapathy, R.Canal, D.Alexandrescu, E.Costenaro, A.Gonzalez and A.Rubio, INFORMER: An Integrated Framework for Early-Stage Memory Robustness Analysis, In Proceedings of the Design, Automation and Test in Europe Conference (DATE'14), Dresden (Germany), March 2014.

  • A. Brankovic, K. Stavrou, E. Gibert, and A. González. 2014. Warm-Up Simulation Methodology for HW/SW Co-Designed Processors, In Proceedings of Annual IEEE/ACM International Symposium on Code Generation and Optimization (CGO '14). Orlando, USA, February 2014.

  • R. Meseguer, C. Molina , S. F. Ochoa, R. Santos, Energy-Aware Topology Control Strategy for Human-Centric Wireless Sensor Networks, Sensors Journal, Volume 14, pp. 2619-2643, February 2014. (paper)


2013

  • R. Kumar, A. Martínez, and A. González. Speculative Dynamic Vectorization to Assist Static Vectorization in a HW/SW Co-designed Environment. In the Proceedings of 20th International Conference on High Performance Computing (HiPC 2013) Bangalore, India, December 18-21, 2013.


  • E. Amat, A. Calomarde, C.G. Almudéver, N. Aymerich, R. Canal, A. Rubio, FinFET and III-V/Ge technology impact on 3T1D cell behavior, Intel Ireland Research Conference (IIRC), Dublin (Ireland), November 2013.


  • R. Kumar, A. Martínez, and A. González. Speculative Dynamic Vectorization to Assist Static Vectorization in a HW/SW Co-designed Environment. in Hipeac Compiler, Architecture and Tools Conference at Haifa, Israel, November 18-19, 2013. (presentation only).


  • R. Kumar, A. Martínez, and A. González. Vectorizing for Wider Vector Units in a HW/SW Co-designed Environment. In the Proceedings of 15th International Conference on High Performance Computing and Communications (HPCC 2013) Zhangjiajie, China, November 13-15, 2013


  • R. Kumar, A. Martínez, and A. González. Dynamic Selective Devectorization for Efficient Power Gating of SIMD units in a HW/SW Co-designed Environment. In the Proceedings of the 25th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2013).Porto de Galinhas, Pernambuco, Brazil, October 23-26, 2013.(Paper)


  • J.M. Arnau, J.M. Parcerisa and P. Xekalakis. Parallel Frame Rendering: Trading Responsiveness for Energy on a Mobile GPU. In the Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2013.


  • E. Amat, C.G. Almudéver, N. Aymerich, R. Canal, A. Rubio, Variability Robustness Enhancement for 7nm FinFET 3T1D-DRAM Cells, IEEE 55th International Midwest Symposium on Circuits and systems (MWSCAS 2013) Columbus (Ohio, USA), August 2013.


  • G. Upasani, X. Vera and A. Gonzalez. Reducing DUE-FIT of Caches by Exploiting Acoustic Wave Detectors for Error Recovery. In Proceedings of the 19th IEEE International On-Line Testing Symposium (IOLTS'13), July 2013.


  • N. Jing, Y. Shen, Y. Lu, S. Ganapathy, Z. Mao, M. Guo, R. Canal and X. Liang, An Energy-Efficient and Scalable eDRAM-Based Register File Architecture for GPGPU, in Proceedings of the International Symposium on Computer Architecture (ISCA'13), Tel-Aviv (Israel), June 2013


  • J.M. Arnau, J.M. Parcerisa and P. Xekalakis. TEAPOT: A Toolset for Evaluating Performance, Power and Image Quality on Mobile Graphics Systems. In the Proceedings of the International Conference on Supercomputing (ICS), June 2013.


  • A. Brankovic, K. Stavrou, E. Gibert, and A. González. Performance analysis and predictability of the software layer in dynamic binary translators/optimizers. In Proceedings of the ACM International Conference on Computing Frontiers (CF '13). Ischia, Italy, May 2013.


  • E. Amat, C.G. Almudever, N. Aymerich, R. Canal and A. Rubio, Impact of FinFET technology introduction in the 3T1D-DRAM memory cell, IEEE Transactions on Device and Materials Reliability v.13, n. 1, pp. 287-292, March 2013 (paper)


  • E. Amat, C.G. Almudever, N. Aymerich, R. Canal and A. Rubio, Variability mitigation mechanisms in scaled 3T1D DRAM memories to 22nm and beyond, IEEE Transactions on Device and Materials Reliability v.13, n.1, pp. 103-109, March 2013, (paper)


  • E.Herrero, J.González, R.Canal and D.Tullsen, Thread Row Buffers: Improving memory performance isolation and throughput in multiprogrammed environments, IEEE Transactions on Computers, vol. 62, no. 9, pp. 1879-1892, September 2013 (paper)


  • S.Ganapathy, R.Canal, A.Gonzalez and A.Rubio, Effectiveness of Hybrid Recovery Techniques on Parametric Failures, In Proceedings of the International Symposium on Quality Electronic Design (ISQED'13), Santa Clara (USA), March 2013


  • J. Carretero, E. Herrero, M. Monchiero, T. Ramirez and X. Vera, Capturing Vulnerability Variations for Register Files, In Proceedings of the IEEE Design, Automation and Test in Europe Conference (DATE’13), Grenoble (France), March 2013


  • V. Lorente, A. Valero, J. Sahuquillo, S. Petit, R. Canal, P. Lopez, J. Duato, Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes, In Proceedings of the IEEE Design, Automation and Test in Europe Conference (DATE’13), Grenoble (France), March 2013


  • Z. Jakšić, R. Canal, Comparison of SRAM Cells for 10nm SOI FinFETs Under Process and Environmental Variations, IEEE Transactions on Electron Devices v.60 n.1 pp.49-55 January 2013 (paper)


  • J. Lira, C. Molina, R. Rakvic and A. González, Replacement Techniques for Dynamic NUCA Cache Designs on CMPs, The Journal of Supercomputing: Volume 64, Issue 2 (2013), Page 548-579 (Paper)

2012

  • Z. Jakšić, R. Canal, Effects of FinFET Technology Scaling on 3T and 3T1D Cell Performance Under Process and Environmental Variations, 3rd Workshop on Workshop on Resilient Architectures, in conjunction with the 45th Annual IEEE/ACM International Symposium on Microarchitecture, Vancouver (Canada), December 2012 (paper)


  • E. Amat, C.G. Almudéver, N. Aymerich, R. Canal, A. Rubio, Mitigation strategies of the variability in 3T1D cell memories scaled beyond 22nm, 27th Conference on Design of Circuits and Integrated Systems (DCIS 2012), Avignon (France), November 2012 (Best Paper Award)


  • E. Amat, C.G. Almudéver, N. Aymerich, R. Canal, A. Rubio, Impact of Bulk/SOI 10nm FinFETs on 3T1D-DRAM cell performance, 11th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT 2012), Xian (China), October 2012


  • Z. Jakšić, R. Canal, Enhancing 3T DRAMs for SRAM Replacement Under 10nm Tri-Gate SOI FinFETs, In Proceedings of the 30th International Conference on Computer Design (ICCD'12), Montreal (Canada), September 2012 (Paper)

  • S.Ganapathy, R.Canal, D.Alexandrescu, E.Costenaro, A.Gonzalez and A.Rubio, A Novel Variation-Tolerant 4T-DRAM Cell with Enhanced Soft-Error Tolerance, In Proceedings of the 30th International Conference on Computer Design (ICCD'12), Montreal (Canada), September 2012 (Paper)


  • R. Meseguer, C. Molina, S. Ochoa, R. Santos, Reducing Energy Consumption in Human-Centric Wireless Sensor Networks. In Proceedings of the IEEE International Conference on Systems, Man, and Cybernetics, (SMC’12), Seoul (Korea), October 2012. (Paper),(Slides)


  • R. Kumar, A. Martínez, and A. González. Speculative Dynamic Vectorization for HW/SW Co-designed Processors. In Proceedings of the 21st international conference on Parallel architectures and compilation techniques (PACT '12). Minneapolis, MN, USA, September 2012. (As poster paper) (Paper), (Poster)


  • G. S. Shenoy, J. Tubella, and A. Gonzalez. Improving the Resilience of an IDS against Performance Throttling Attacks. In Proceedings of the 8th International Conference on Security and Privacy in Communication Networks (SECURECOMM-2012), September 2012. (Paper)

  • G. S. Shenoy, J. Tubella, and A. Gonzalez. Improving the Performance Efficiency of an IDS by Exploiting Temporal Locality in Network Traffic. In Proceedings of the 20th International Symposium on Modeling, Analysis, and Simulation  of Computer and Telecommunication Systems (MASCOTS-2012), August 2012.(Paper).

  • J. Cano, A. Brankovic, R. Kumar, D. Zivanovic, D. Pavlou, K. Stavrou, E. Gibert, A. Martínez, G. Dot, F. Latorre, A. Barceló, and A. González. Modelling HW/SW Co-Designed Processors. In Eighth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES 2012), Fiuggi, Italy, July 2012. (Paper), (Poster)


  • E. Amat, A. Asenov, R. Canal, B. Cheng, J-L. Cruz, Z. Jakšić, M. Miranda, A. Rubio, P. Zuber, Analysis of FinFET Technology on Memories (invited paper), 18th IEEE International On-Line Testing Symposium (IOLTS'12), Sitges (Catalonia), June 2012 (Paper)


  • A. Brankovic, K. Stavrou, E. Gibert, A. Gonzalez. Analysis of CPI Variance for Dynamic Binary Translators/Optimizers Modules. In Proceedings of the 5th Workshop on Architectural and Microarchitectural Support for Binary Translation (AMAS-BT'12), held in conjuction with the 39th International Symposium on Computer Architecture (ISCA-39), 9-13 June, 2012 in Portland, OR, USA.

  • G. Upasani, X. Vera and A. Gonzalez. Setting an Error Detection Infrastructure with Low Cost Acoustic Wave Detectors. In Proceedings of the 39th International Symposium on Computer Architecture (ISCA'12), June 2012.


  • J.M. Arnau, J.-M. Parcerisa, P. Xekalakis. Boosting Mobile GPU Performance with a Decoupled Access/Execute Fragment Processor. In Proceedings of the 39th International Symposium on Computer Architecture (ISCA'12), June 2012. (Paper)


  • R. Martínez, J. M. Claver, F. J. Alfaro, and J. L. Sánchez. Hardware implementation study of several new egress link scheduling algorithms. Journal of Parallel and Distributed Computing,  available online May 2012.


  • G. S. Shenoy, J. Tubella, and A. Gonzalez. Hardware/Software Mechanisms for Protecting an IDS against Algorithmic Complexity Attacks. In Proceedings of the 2012 International Workshop on Security and Trust of Distributed Networking Systems (STDN-2012), May 2012.(Paper)


  • Z. Jakšić, R. Canal. Enhancing 6T SRAM Cell Stability by Back Gate Biasing Techniques for 10nm SOI FinFETs under Process and Environmental Variations. 19th International Conference on Mixed Design of Integrated Circuits and Systems, Warsaw (Poland), May 2012.(paper)


  • E. Amat, C.G. Almudéver, N. Aymerich, R. Canal, A. Rubio. Strain Relevance on the Improvement of the 3T1D Cell Performance. 19th International Conference on Mixed Design of Integrated Circuits and Systems, Warsaw (Poland), May 2012.(paper)


  • T. Ramírez, E. Herrero, N. Axelos, J. Carretero, N. Foutris, D. Sanchez, X. Vera. Mitigating Lower Layer Failures with Adaptive System Reconfiguration. 19th International Conference on Mixed Design of Integrated Circuits and Systems, Warsaw (Poland), May 2012. (paper)


  • E. Herrero, J. González, R. Canal, Distributed Cooperative Caching: An Energy Efficient Memory Scheme for Chip Multiprocessors, IEEE Transactions on Parallel and Distributed Systems, v. 23, n. 5, pp. 853-861, May 2012. (paper)


  • N.Aymerich, S.Ganapathy, A.Rubio, R.Canal, A.Gonzalez. Impact of Positive Bias Temperature Instability (PBTI) on 3T1D-DRAM Cells. Integration, the VLSI Journal, Integration, the VLSI Journal v.45, n.3, pp. 246–252, June 2012.(paper)


  • M. Pons, M. Morgan, C. Piguet. Fixed Origin Corner Square Inspection Layout Regularity Metric. Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012, pp.1397-1402, 12-16 March 2012.


  • G. S. Shenoy, J. Tubella, and A. Gonzalez. Exploiting Temporal Locality in Network Traffic Using Commodity Multi-cores. In Proceedings of the 2012 IEEE International Symposium on  Performance Analysis of Systems and Software (ISPASS-2012), April 2012 (accepted as a short paper). (paper)


  • D. Pavlou, E. Gibert, F. Latorre, A. González. DDGacc: Boosting Dynamic DDG-based Binary Optimizations through Specialized Hardware Support. In Proceedings of  the 8th Annual International Conference on Virtual Execution Environments, (VEE 2012), London (UK), March 2012.


  • J. Lira, T. M. Jones, C. Molina, A. González. The Migration Prefetcher: Anticipating Data Promotion in Dynamic NUCA Caches. In Proceedings of the 7th International Conference on High-Performance and Embedded Architectures and Compilers, (HIPEAC’12), Paris (France), January 2012. Also appears on the ACM Transactions on Architecture and Code Optimization (TACO), Special Issue on High-Performance and Embedded Architectures and Compilers, Vol 8, No 4. (Paper),(Slides)

2011

  • J. Lira, C. Molina, D. Brooks, A. González. Implementing a hybrid SRAM / eDRAM NUCA architecture. In Proceedings of the 18th Annual International Conference on High Performance Computing (HiPC'11), Bangalore (India), December 2011. (Paper),(Slides)

 

  • N. Fourtris, D. Gizopoulos, M. Psarakis, X. Vera, A. Gonzalez. Accelerating Microprocessor Silicon Validation by Exposing ISA Diversity. In Proceedings of 44th International Symposium on Microarchitecture (MICRO) 2011..


  • N. Aymerich, S. Ganapathy, A.Rubio, R. Canal, A. González, Impact of Positive Bias Temperature Instability (PBTI) on 3T1D-DRAM Cells, Integration, the VLSI Journal, Elsevier. December 2011 (Paper)


  • J. Carretero, J. Abella,  X. Vera, P. Chaparro. Control-Flow Recovery Validation Using Microarchitectural Invariants. In Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT'11), Vancouver (Canada), October 2011


  • S.Ganapathy, R.Canal, A.Gonzalez and A.Rubio, Dynamic Fine-Grain Body Biasing of Caches with Latency and Leakage 3T1D-Based Monitors, In Proceedings of the 30th International Conference on Computer Design (ICCD'11), Amherst (USA), October 2011 (paper)


  • J. Lira, T. M. Jones, C. Molina, A. González. Beforehand Migration on D-NUCA Caches. In Proceedings of the 20th International Conference on Parallel Architectures and Compilation Techniques (PACT'11), Galveston Island (USA), October 2011. (Paper),(Poster)

  • A. Deb, J. M. Codina and A. González, A HW/SW Co-designed Programmable Functional Unit, In IEEE Computer Architecture Letters (CAL’11), October 2011, (Paper).

  • A. Deb, J. M. Codina and A. González, A Power-efficient Co-designed Out-of-Order Processor, In Proceedings of the 23rd International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'11), Vitória, Espírito Santo (Brasil), October 2011. (Paper).

 

  • M. Pons, F. Moll, A. Rubio, J. Abella, X. Vera, A. Gonzalez. Design of Complex Circuits using the VIA-Configurable Transistor Array Regular Layout Fabric, In Proceedings of IEEE International SoC Conference , September 2011


  • N. Aymerich, A. Asenov, A. Brown, R. Canal, J. Figueras, A. Gonzalez, E. Herrero, M. Miranda, P. Pouyan, T. Ramirez, A. Rubio, I. Vatajelu, X. Vera, P. Zuber, New Reliability Mechanisms in Memory Design for sub-22nm Technologies, In Proceedings of the IEEE International Online Testing Symposium (IOLTS’11), Athens(Greece), July 2011.(paper)


  • D. Pavlou, A. Brankovic, R. Kumar, M. Gregori, K. Stavrou, E. Gibert, A. Gonzalez. DARCO: Infrastructure for Research on HW/SW co-designed Virtual Machines. In Proceedings of the 4th Workshop on Architectural and Microarchitectural Support for Binary Translation (AMAS-BT'11), held in conjuction with the 38th International Symposium on Computer Architecture (ISCA-38), San Jose, California, USA, June 4, 2011.(Paper)


  • R. Canal, A. Rubio, A. Asenov, A. Brown, M. Miranda, P. Zuber, A. Gonzalez and X. Vera; TRAMS Project: Variability and Reliability of SRAM Memories in sub-22 nm Bulk-CMOS Technologies; Proceedings of the 2nd European Future Technologies Conference and Exhibition 2011 (FET 11), Procedia Computer Science, Volume 7, pp. 148-149. 2011 (Paper)
       
  • N.Aymerich, S.Ganapathy, A.Rubio, R.Canal, and A.Gonzalez Impact of Positive Bias Temperature Instability (PBTI) on 3T1D-DRAM Cells, In Proceedings of the 21st Great Lakes Symposium on Very Large Scale Integration (GLSVLSI'11), Lausanne(Switzerland), May 2011 (paper)

  • A. Deb, J. M. Codina and A. González, SoftHV : A HW/SW Co-designed Processor with Horizontal and Vertical Fusion, In Proceedings of the 8th ACM International Conference on Computing Frontiers (CF'11), Ischia (Italy), May 2011. (Paper).


  • G. S. Shenoy, J. Tubella, and A. González. A Performance and Area Efficient Architecture for Intrusion Detection Systems. In Proceedings of the 25th IEEE International Parallel and Distributed Processing Symposium (IPDPS'11), Anchorage (Alaska), May 2011. (Paper).


  • J. Lira, C. Molina and A. González, HK-NUCA: Boosting Data Searches in Dynamic Non-Uniform Cache Architectures for Chip Multiprocessors, In Proceedings of the 25th IEEE International Parallel and Distributed Processing Symposium (IPDPS'11), Anchorage (USA), May 2011. (Paper),(Slides)


  • I. Bhagat, E.Gibert, J. Sánchez, A. González, Global Productiveness Propagation: A Code Optimization Technique to Speculatively Prune Useless Narrow Computations, In Proceedings of the ACM SIGPLAN/SIGBED 2011 conference on Languages, compilers, and tools for embedded systems, LCTES 2011, Chicago, IL, USA, April 11-14, 2011


  • I. Bhagat, E.Gibert, J. Sánchez, A. González, Eliminating Non-Productive Memory Operations in Narrow-Bitwidth Architectures, In Proceedings of the 9th Workshop on Optimizations for DSP and Embedded Systems (ODES-9), held in conjunction with the 9th International Conference on Code Generation and Optimization (CGO'11), Chamonix, France, April 2011.


  • M. Pons, E. Barajas, D. Mateo, J.L. González, F. Moll, A. Rubio, J. Abella, X. Vera, A. González. Fast time-to-market with Via-Configurable Transistor Array regular fabric: a Delay-Locked Loop design case study, In Proceedings of International Conference on Design & Technology of Integrated Systems in nanoscale era (DTIS), 2011


  • A. Deb, J. M. Codina and A. González, A Co-designed HW/SW Approach to General Purpose Program Acceleration using a Programmable Functional Unit, In Proceedings of the 15th Workshop on Interaction between Compilers and Computer Architecture (INTERACT'11), held in conjunction with the 17th International Symposium on High-Performance Computer Architecture (HPCA'11), San Antonio (Texas), February 2011. (Paper)


  • J. Bobba, M. Lupon, M. D. Hill, and D. A. Wood. Safe and Efficient Supervised Memory Systems. In Proceedings of the 17th IEEE International Symposium on High Performance Computer Architecture (HPCA'11). February 2011. (Paper)


  • J. Carretero, X. Vera, J. Abella, T. Ramírez, M. Monchiero, A. Gonzalez. Hardware/Software Based Diagnosis of Load-Store Queues Using Expandable Activity Logs. In Proceedings of the 17th IEEE International Symposium on High Performance Computer Architecture (HPCA'11). February 2011.


  • R. Ranjan, F. Latorre, P. Marcuello and A. González. Fg-STP: Fine Grained Single Thread Partitioning for Multicores. In Proceedings of the 17th IEEE International Symposium on High Performance Computer Architecture (HPCA'11). February 2011.


  • R. Rakvic, R. W. Ives, J. Lira, C. Molina, Case for an FPGA-Multi-Core Hybrid Machine for an Image Processing Application, International Society for Optics and Photonics, Journal on Electronic Imaging, SPIE Digital Library (ISSN:1017-9909), Vol 20, Issue 1, January 2011. (Paper)


2010

  • E. Quiñones, J.-M. Parcerisa and A. González. Leveraging Register Windows to Reduce Physical Registers to the Bare Minimum. IEEE Transactions on Computers (TC), 59 (12):1598-1610. December 2010.


  • M. Lupon, G. Magklis, A. González. A Dynamically Adaptable Hardware Transactional Memory. In Proceedings of the 43rd International Symposium on Microarchitecture (MICRO'10), Atlanta (USA), December 2010. (Paper)


  • R. Rakvic, Q. Cai, J. González, G. Magklis, P. Chaparro, and A. González. Thread-management techniques to maximize efficiency in multicore and simultaneous multithreaded microprocessors. ACM Trans. Archit. Code Optim. 7, 2, Article 9 (October 2010).


  • E. Herrero, J. González, R. Canal. An application-aware adaptive cache organization for tiled micro architectures. In Intel European Research and Innovation Conference (ERIC'10), Braunschweig (Germany), September 2010.


  • M.Pons, F.Moll, A.Rubio, J.Abella, X.Vera, A.González. VCTA: a Via-Configurable Transistor Array Regular Fabric. In 18th IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC'10), Madrid (Spain), September 2010.


  • S.Ganapathy, R.Canal, A.Gonzalez, A.Rubio. Cache Design Under Spatio-Temporal Variability. In Intel European Research and Innovation Conference (ERIC'10), Braunschweig (Germany), September 2010.


  • E. Medina, R. Meseguer, C. Molina and D.Royo. OLSRp: Predicting Control Information to Achieve Scalability in OLSR Ad Hoc Networks. In Proceedings of the 2nd International ICST Conference on Mobile Networks and Management, (MONAMI’10), Santander (Spain), September 2010. (Paper),(Slides)


  • E. Herrero, J. González, R. Canal. Power-Efficient Spilling Techniques for Chip Multiprocessors, In Proceedings of the International Conference on Parallel and Distributed Computing, (EURO-PAR'10), Ischia (Italy), September 2010.


  • S.Ganapathy, R.Canal, A. González, A. Rubio. MODEST: A Model for Energy Estimation under Spatio-Temporal Variability, In Proceedings of the 2010 IEEE/ACM International Symposium on Low Power Electronic Design (ISLPED'10), Austin (USA), August 2010


  • J. Lira, C. Molina and A. González, The Auction: Optimizing Banks Usage in Non-Uniform Cache Architectures, In Proceedings of the 24th International Conference on Supercomputing (ICS'10), Tsukuba (Japan), June 2010. (Paper),(Slides)


  • E. Herrero, J. González, R. Canal. Elastic Cooperative Caching: An Autonomous Dynamically Adaptive Memory Hierarchy for Chip Multiprocessors. In Proceedings of the 37th International Symposium on Computer Architecture (ISCA'10), Saint-Malo (France), June 2010. (Paper)


  • Javier Carretero, Xavier Vera, Pedro Chaparro, Jaume Abella: Microarchitectural Online Testing for Failure Detection in Memory Order Buffers. IEEE Trans. Computers 59(5): 623-637 (2010)


  • I. Bhagat, E.Gibert, J. Sánchez, A. González, Global Productiveness Propagation: A Code Optimization Technique to Speculatively Prune Useless Narrow Computations, In Proceedings of the 8th Workshop on Optimizations for DSP and Embedded Systems (ODES-8), held in conjunction with the 8th International Conference on Code Generation and Optimization (CGO'10), Toronto, Canada, April 2010.


  • Jaume Abella, Javier Carretero, Pedro Chaparro, Xavier Vera: The split register file. In Proceedings of the 2010 IEEE Design, Automation and Test in Europe Conference (DATE’10), Dresden (Germany), March 2010.


  • S. Ganapathy, R. Canal, A. González, A. Rubio, Circuit Propagation Delay Estimation Through Multivariate Regression-Based Modeling Under Spatio-Temporal Variability, In Proceedings of the 2010 IEEE Design, Automation and Test in Europe Conference (DATE’10), Dresden (Germany), March 2010.


  • J. Abella, P. Chaparro, X. Vera, J. Carretero, A. González, High-Performance Low-Vcc In-Order Core, In Proceedings of the 16th International Symposium on High-Performance Computer Architecture (HPCA'10), Bangalore (India), January 2010.


2009

  • J. Abella, J. Carretero, P. Chaparro, X. Vera, A. González, Low Vccmin Fault-Tolerant Cache with Highly Predictable Performance, In Proceedings of the 42nd International Symposium on Microarchitecture (MICRO'09), New York (New York), December 2009


  • R. Ranjan, P. Marcuello, F. Latorre and A. González. P-Slice Based Efficient Speculative Multithreading. In the Proceedings of the 16th International Conference on High Performance Computing (HiPC'09), Kochi, India, December 2009


  • A. Valero, J. Sahuquillo, S. Petit, V. Lorente, R. Canal, P. Lopez and J. Duato, An hybrid eDRAM/SRAM macrocell to implement first-level data caches, In Proceedings of the 42nd International Symposium on Microarchitecture (MICRO'09), New York (New York), December 2009


  • P. Chaparro, J. Gonzalez, Q. Cai and G. Chrysler. Dynamic Thermal Management using Thin-Film Thermoelectric Cooling, International Symposium on Low Power Electronics and Design (ISLPED), 2009.


  • J. Lira, C. Molina and A. González, LRU-PEA: A Smart Replacement Policy for Non-Uniform Cache Architectures on Chip Multiprocessors, In Proceedings of the 27th International Conference on Computer Design (ICCD'09), Lake Tahoe (USA), October 2009. (Paper),(Slides)


  • M. Monchiero, R. Canal and A. González, Using Coherence Information and Decay Techniques to Optimize L2 Cache Leakage in CMPs, IEEE 38th International Conference on Parallel Processing (ICPP), Vienna (Austria), September 2009


  • R. Martinez, J.M. Claver, F.J. Alfaro, and J.L.Sanchez, Hardware implementation study of the Deficit Table egress link scheduling algorithm, IEEE 38th International Conference on Parallel Processing (ICPP), Vienna (Austria), September 2009.


  • J. Lira, C. Molina and A. González, Performance Analysis of Non-Uniform Cache Architecture Policies for Chip-Multiprocessors Using the Parsec V2.0 Benchmark Suite, In Proceedings of the XX Jornadas de Paralelismo, A Coruña (Spain), September 2009. (Paper),(Slides)


  • M. Lupon, G. Magklis and A. González, FASTM: A Log-based Hardware Transactional Memory with Fast Abort Recovery, In Proceedings of the 18th International Conference on Parallel Architectures and Compilation Techniques, (PACT'09), Raleigh (North Carolina), September 2009. (Paper)


  • C. Madriles, P. López, J.M. Codina, E. Gibert, F. Latorre, A. Martínez, R. Martínez, A. González, Anaphase: A Fine-Grain Thread Decomposition Scheme for Speculative Multithreading, In Proceedings of the 18th International Conference on Parallel Architectures and Compilation Techniques, (PACT'09), Raleigh (North Carolina), September 2009. (Paper)

 

  • J. Lira, C. Molina and A. González, Last Bank: Dealing with Address Reuse in Non-Uniform Cache Architecture for CMPs, In Proceedings of the International Conference on Parallel and Distributed Computing, (EURO-PAR'09), Delft, (The Netherlands), August 2009. (Paper),(Slides)


  • R. Martinez, F.J. Alfaro, J.L.Sanchez, and J.M. Claver. Hardware implementation study of the SCFQ-CA and DRR-CA scheduling algorithms. In Proceedings of the European Conference on Parallel Computing (Euro-Par), Lecture Notes in Computer Science (LNCS), ISSN 0302-9743 , vol 5704, August 2009.


  • J. Carretero, P. Chaparro, J. Abella, X. Vera, A. González, End-to-End Register Data-Flow Continuous Self-Test, In Proceedings of the 36th International Symposium on Computer Architecture (ISCA'09), Austin (Texas), June 2009 (a version of this paper has been published in the internal Intel conference Intel Design and Test Technolgy Conference 2008)


  • C. Madriles, P. López, J. M.Codina, E. Gibert, F. Latorre, A. Martínez, R. Martínez, A. González, Boosting Single-Thread Performance in Multi-Core Systems through Fine-Grain Multithreading, In Proceedings of the 36th International Symposium on Computer Architecture (ISCA'09), Austin (Texas), June 2009. (Paper),(Slides)


  • X. Vera, J. Abella, J. Carretero, P. Chaparro, A. González, Online Error Detection and Correction of Erratic Bits in Register Files, In Proceedings of the 15th International On-Line Testing Symposium (IOLTS'09), Lisbon (Portugal), June 2009


  • M. Pons, F.Moll, A.Rubio, J.Abella, X.Vera, A.González. Addressing Process Variations with VCTA at DATE Workshop on Process Variability: New Techniques for the Design and Test of Nanoscale Electronics, Nice (France), April 2009 (poster presentation).


  • J. Carretero, X. Vera, J. Abella, P. Chaparro, A. González, A Low-Overhead Technique to Protect the Issue Control Logic against Soft Errors, In the 5th Workshop on Silicon Errors in Logic - System Effects (SELSE'09), Stanford (California), March 2009


  • J. Lira, C. Molina and A. González, Analysis of Non-Uniform Cache Architecture Policies for Chip-Multiprocessors Using the Parsec Benchmark Suite, In Proceedings of the 2nd Workshop on Managed Many-Core Systems (MMCS'09), held in conjunction with the 14th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'09), Washington D.C, (USA), March 2009. (Paper),(Slides)


  • M.Pons, F.Moll, J.Abella. Variations Aware Circuit Designs for Microprocessors. In Proceedings of the 1st Barcelona Forum on Ph.D. Research in Electronic Engineering, 2009.


2008

  • J. Abella, X. Vera, O. Unsal, O. Ergin, A. González, J.W. Tschanz, Refueling: Preventing Wire Degradation due to Electromigration, IEEE Micro, special issue on Existential Architectures - The Metaphysics of Computer Design, November-December 2008


  • J. Carretero, X. Vera, P. Chaparro, J. Abella, On-line Failure Detection in Memory Order Buffers, In Proceedings of the International Test Conference (ITC'08), Santa Clara (California), October 2008


  • P. Chaparro, J. Abella, J. Carretero, X. Vera, Issue System Protection Mechanisms, In Proceedings of the 26th International Conference on Computer Design (ICCD'08), Lake Tahoe (California), October 2008


  • Q. Cai, J.González, R. Rakvic, G. Magklis, P. Chaparro and A.González, Meeting Points: Using Thread Criticality to Adapt Multicore Hardware to Parallel Regions, In Proceedings of the17th International Conference on Parallel Architectures and Compilation Techniques, (PACT'08), Toronto (Canada), October 2008.


  • J. Gonzalez, Q. Cai, P. Chaparro, G. Magklis, R. Rakvic and A. Gonzalez.Thread Fusion, International Symposium on Low Power Electronics and Design (ISLPED), 2008.


  • E.Herrero, J.González and R.Canal, Distributed Cooperative Caching, In Proceedings of the17th International Conference on Parallel Architectures and Compilation Techniques, (PACT'08), Toronto (Canada), October 2008.


  • M. Lupon, G. Magklis, A. González, Version Management Alternatives for Hardware Transactional Memory, In Proceedings of the 9th Workshop on Memory Performance: Dealing with Applications, Systems and Architecture, (MEDEA'08), Toronto (Canada), October 2008. (Paper)


  • D.Jiménez-González, C.Álvarez, D.López, J.-M.Parcerisa, J.Alonso, C.Pérez, R.Tous, P.Barlet, M.Fernández and J.Tubella, Work in Progress--Improving Feedback Using an Automatic Assessment Tool, In Proceedings of the 38th. Annual Frontiers in Education Conference (FIE 2008), Saratoga Springs (New York), October 2008


  • J. Carretero, X. Vera, J. Abella, P. Chaparro, A. González, A Low-Overhead Technique to Protect the Issue Control Logic against Soft Errors, In Proceedings of the XIX Jornadas de Paralelismo, Castellón (Spain), September 2008


  • X.Liang, R.Canal, G.Y. Wei, D. Brooks, DRAM-based On-Chip Cache Architectures to Combat Process Variations, Intel 2008 European Research and Innovation Conference, Leixlip (Ireland), September 2008


  • E.Herrero, J.González and R.Canal, A Scalable and Power-Efficient Memory Hierarchy for Multicore Architectures, Intel 2008 European Research and Innovation Conference, Leixlip (Ireland), September 2008


  • J. Abella, J. Carretero, P. Chaparro, X. Vera, A. González, Dynamic Errors: Symptoms and Solutions, Presentation in the Industrial Track of the 14th International European Conference on Parallel and Distributed Computing (EURO-PAR'08), Las Palmas de Gran Canaria (Spain), August 2008


  • J. Abella, P. Chaparro, X. Vera, J. Carretero, A. González, On-Line Failure Detection and Confinement in Caches, In Proceedings of the 14th International On-Line Testing Symposium (IOLTS'08), Rodhes (Greece), July 2008


  • R. Martínez, F.J. Alfaro, J.L. Sánchez, A framework to provide Quality of Service over Advanced Switching. IEEE Transactional Parallel and Distributed Systems (TPDS), July 2008


  • C.Álvarez, D.Jiménez-González, D.López, J.Alonso, R.Tous, J.-M. Parcerisa, P.Barlet, M.Fernández, J.Tubella and C.Pérez, SISA-EMU: feedback automático para ensamblador, in Proceedings of the XIV Jornadas de Enseñanza Universitaria de la Informática (JENUI 2008), Granada (Spain), July 2008


  • C. Madriles, C. García-Quiñones, J. Sánchez, P. Marcuello, A. González, D. Tullsen, H. Wang and J.P. Shen, Mitosis: A Speculative Multithreaded Processor based on Precomputation Slices, in IEEE Transactions On Parallel and Distributed Systems, Vol. 19, Number 7, July 2008. (Paper)


  • M. Monchiero, R. Canal, A. González, Power/Performance/Thermal Design Space Exploration for Multicore Architectures, IEEE Transactions on Parallel and Distributed Systems v. 19 n. 5 pp.666-681, May 2008


  • Q. Cai, J. M. Codina, J.González and A.González, A Software-Hardware Hybrid Steering Mechanism for Clustered Microarchitectures, 22nd IEEE International Parallel and Distributed Processing Symposium (IPDPS), April 2008.


  • P. Chaparro, J. Carretero, J. Abella, X. Vera, Soft-Error Protection Mechanisms for In-Order Cores, In the 4th Workshop on Silicon Errors in Logic - System Effects (SELSE'08), Austin (Texas), March 2008


  • C.Molina, J.Tubella and A.González, Reducing Misspeculation Penalty in Trace Level Speculative Multithreaded Architectures, Lecture Notes in Computer Sciences, Springer-Verlag Heidelberg (ISSN 0302-9743), vol 4759, January 2008. (Paper)


  • X.Liang, R.Canal, G.Y. Wei, D. Brooks, Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability, IEEE Micro Micro's Top Picks from Computer Architecture Conferences, v.28 n.1 pp.60-68 Jan/Feb 2008


Before 2008